@timsifive we are debugging intermittent failures.

Fix MulticoreRunHaltStepiTest

The test actually wasn't checking interrupt counts at all. Fixing it
required some other changes:
Make sure all harts get to run
Add some retries, since on a loaded machine against spike both harts
might not get to run, even if you give spike a generous amount of time
to do so.

Mark more Debug tests as "Single Hart"

* [rv64ua/lrsc] Initialize memory read out.

Even though the load contents are discarded, this un-initialized memory value
can lead to a divergence for co-simulation between two different RISC-V designs.

* [rv64ua/lrsc] Use .skip instead of .align.

debug: need to clear satp before changing priv

ISA Manual does not require this register to be reset, and attempting to execute code with VM on when VM hasn't been set up is going to just lead to sadness.

Delete E300Sim.py

debug: add missing align directive on trap_entry

This file is wrong (the .cfg file isn't right) and not used by anything.

Compute gdb command timeout based on ops estimate

The caller of gdb.command() should estimate how much work gdb needs to
do, and testlib then scales this up proportional to the general gdb
timeout we configured. This hopefully allows us to configure a tighter
timeout, so we don't have to have a multi-hour timeout just for
something that takes long like `load` on a really slow simulator.

Hopefully this addresses #122.

Also halt instead of reset spike targets, which tests a more complicated
code path.

This makes it much easier to look at a log if you see a failure
scrolling by on your terminal.

See https://github.com/riscv/riscv-isa-manual/commit/0472bcdd166f45712492829a250e228bb45fa5e7

Update Makefile to allow for RISCV_PREFIX to be set by the configure 

See https://github.com/riscv/riscv-isa-manual/pull/139

It's an optional register.

Specifically, make sure that after resuming all cores, and halting core
0, that OpenOCD's poll() doesn't mess up the currently selected hart to
the point where memory accesses intended for core 0 go to core 1.

OK'd by @palmer-dabbelt 

Cover all combinations of 32,64 bit XLEN with F and FD extensions.

Finishes Issue https://github.com/riscv/riscv-openocd/issues/110

I hope to use this in riscv-tools' regression.sh.

tests: bump env to pick up new names for CSRs