ISA Manual does not require this register to be reset, and attempting to execute code with VM on when VM hasn't been set up is going to just lead to sadness.

Delete E300Sim.py

debug: add missing align directive on trap_entry

This file is wrong (the .cfg file isn't right) and not used by anything.

Compute gdb command timeout based on ops estimate

The caller of gdb.command() should estimate how much work gdb needs to
do, and testlib then scales this up proportional to the general gdb
timeout we configured. This hopefully allows us to configure a tighter
timeout, so we don't have to have a multi-hour timeout just for
something that takes long like `load` on a really slow simulator.

Hopefully this addresses #122.

Also halt instead of reset spike targets, which tests a more complicated
code path.

This makes it much easier to look at a log if you see a failure
scrolling by on your terminal.

See https://github.com/riscv/riscv-isa-manual/commit/0472bcdd166f45712492829a250e228bb45fa5e7

Update Makefile to allow for RISCV_PREFIX to be set by the configure 

See https://github.com/riscv/riscv-isa-manual/pull/139

It's an optional register.

Specifically, make sure that after resuming all cores, and halting core
0, that OpenOCD's poll() doesn't mess up the currently selected hart to
the point where memory accesses intended for core 0 go to core 1.

OK'd by @palmer-dabbelt 

Cover all combinations of 32,64 bit XLEN with F and FD extensions.

Finishes Issue https://github.com/riscv/riscv-openocd/issues/110

I hope to use this in riscv-tools' regression.sh.

tests: bump env to pick up new names for CSRs

gdb gets target XLEN from register width now, so this is taken care of
automatically.

This makes it a little easier to just cut and paste from the log when
reproducing a failure. (The port number still needs changing though.)

Clean up VcsSim init()

Use a unique log file, so you can run multiple instances at once.
Add time out to waiting for the simulator to be ready.

* Probably implemented the changes required to support fadd test for rv32ud

* Created test files in rv32ud, implemented working(?) test for ldst

* fclass, fcvt_w, fmin and recoding seem to be working now

* Got fdiv (and sqrt) tests working

* fmadd tests seem to work

* fcmp works

* [WIP] fcvt working, but lacks a 32-bit implementation of the final test

* Renamed macro TEST_LDST_D32 to TEST_CASE_D32 to indicate that it can be used for more than just LDST

* Added Makefrag for rv32ud tests and included in main isa Makefile

* Don't run 64-bit tests if the defined XLEN is 32

Closes #105.

Closes #103

Fixes --print-failures sometimes not actually printing out details about
failures.

debug: Fix the XLEN command line check