- Jan 20, 2020
-
-
Liu Yibin authored
This patch adds T-HEAD C910 to RV64 platform list in the binary archive script. Signed-off-by:
Liu Yibin <yibin_liu@c-sky.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
-
- Jan 15, 2020
-
-
Liu Yibin authored
Since all harts share the same plic/clint address now, setting them during cold boot is just fine. Signed-off-by:
Liu Yibin <yibin_liu@c-sky.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
-
Liu Yibin authored
Since all harts share the same L2 cache now, there's no need to Enable L2 cache in warm boot. Signed-off-by:
Liu Yibin <yibin_liu@c-sky.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
-
- Jan 10, 2020
-
-
Andreas Schwab authored
Move the .align directives after switching the section. We want to align the start of the current section, not the end of the previous section. This also obsoletes the misguided workaround of disabling relaxation. Signed-off-by:
Andreas Schwab <schwab@suse.de> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
-
Anup Patel authored
With U-Boot v2020.01, the SiFive FU540 DTB required by U-Boot is embedded in U-Boot binary itself so we don't need to do anything special for U-Boot v2020.01 as payload to OpenSBI firmware. This patch updates SiFive FU540 documenation assuming we use latest U-Boot v2020.01 release. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
-
- Jan 09, 2020
-
-
Liu Yibin authored
T-head c910 is a generic FPGA platform so we cannot define PMP configuration for it in OpenSBI because PMP configuration tend to be SOC specific. Signed-off-by:
Liu Yibin <yibin_liu@c-sky.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
-
Abner Chang authored
Add description of using OPENSBI_EXTERNAL_SBI_TYPES in external firmware code base. Signed-off-by:
Abner Chang <abner.chang@hpe.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
-
Abner Chang authored
Add OPENSBI_EXTERNAL_SBI_TYPES macro to allow external definitions of data types and common macros. Also move some common definitions from sbi_bits.h to sbi_types.h. Signed-off-by:
Abner Chang <abner.chang@hpe.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
-
- Jan 08, 2020
-
-
Khem Raj authored
this is a stand-alone/baremetal application, therefore demanding -ffreestanding would help it compile with hosted toolchains e.g. ( linux toolchains ), it also ensures that it won't be using platform optimizations like inlining mem* str* functions which gcc might decide especially with wrapper string functions in opensbi code Signed-off-by:
Khem Raj <raj.khem@gmail.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
-
- Jan 07, 2020
-
-
Anup Patel authored
We add sbi_init_count() API which provides number of times a given HART completed init sequence (warmboot/coldboot). This will be very useful in debugging. With upcoming SBI HSM extension, it will also help in implementing one-time init code for each HART. Signed-off-by:
Anup Patel <anup@brainfault.org> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
-
Anup Patel authored
We should zero-out memory allocated from extra scratch space using sbi_scratch_alloc_offset() API hence this patch. This will not impact performance because we mostly allocate from extra scratch space only at cold boot time. Signed-off-by:
Anup Patel <anup@brainfault.org> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
-
Anup Patel authored
We improve sbi_system_reboot() an sbi_system_shutdown() by: 1. Calling halt IPI to all harts (except current HART) before calling platform reboot/shutdown hook. 2. Calling sbi_exit() instead of sbi_hang() in-case platform reboot/shutdown hook failed. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
-
Anup Patel authored
Instead of doing sbi_hang() we should do sbi_exit() upon halt IPI. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
-
Anup Patel authored
Currently, sbi_hart_wait_for_coldboot() leaves MIE.MSIP bit set when it returns which is not correct because MIE.MSIP should be left enabled only by sbi_ipi_init(). This patch does save/restore of MIE CSR to ensure that MIE CSR is in original state after sbi_hart_wait_for_coldboot() returns. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
-
Anup Patel authored
We add an optional platform irqchip exit hook for exit path handling in sbi_exit() implementation. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
-
Anup Patel authored
We add sbi_ipi_exit() API for exit path handling in sbi_exit() implementation. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
-
Anup Patel authored
We add sbi_timer_exit() API for OpenSBI exit path handling in sbi_exit() implementation. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
-
Anup Patel authored
This patch adds system-level early_exit and final_exit APIs with corresponding platform hooks. These new APIs will be primarily used by sbi_exit() in OpenSBI exit path. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
-
Anup Patel authored
This patch adds initial implementation of sbi_exit() API which can be used to perform OpenSBI exit sequence for current HART. The sbi_exit() implementation will be further extended by subsequent patches. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
-
Anup Patel authored
We remove unnecessary checks related to hart hotplug and disabled hart in coldboot and warmboot init path. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
-
- Jan 02, 2020
-
-
Liu Yibin authored
This commit provides basic support for the Thead/C910 platform. Signed-off-by:
Liu Yibin <yibin_liu@c-sky.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
-
Anup Patel authored
It is possible to have a CLINT implementation which supports only 32bit MMIO accesses on RV64 system so this patch extends our CLINT driver such that platform code can specify whether CLINT supports 64bit MMIO access. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish <Patra<atish.patra@wdc.com> Reviewed-by:
Zong Li <zong.li@sifive.com>
-
- Dec 30, 2019
-
-
Liu Yibin authored
This patch updates FW_JUMP and FW_PAYLOAD documentation for the case where FW_xyz_FDT_ADDR is not specified. Signed-off-by:
Liu Yibin <yibin_liu@c-sky.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
-
- Dec 27, 2019
-
-
Anup Patel authored
The state of a0, a1, and a2 registers in fw_prev_arg1() and fw_next_arg1() is same as passed by previous booting stage so we add this info in comments for both these functions. Signed-off-by:Anup Patel <anup.patel@wdc.com>
-
Liu Yibin authored
Function fw_next_arg1 in firmware/fw_jump.S:59 and firmware/fw_payload.S:63 should return real dtb address(if specified in a1) in a0, in case we don't want to specify FW_xyz_FDT_ADDR when compiling. Signed-off-by:
Liu Yibin <yibin_liu@c-sky.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
-
- Dec 23, 2019
-
-
Atish Patra authored
This patch adds RFENCE extension support in OpenSBI. Signed-off-by:
Atish Patra <atish.patra@wdc.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
-
Atish Patra authored
The hypervisor specification support hfence calls which can be used issue tlb flush requests at both level of address translation. Currently, these requests are issued only via SBI which are defined in v0.2. Signed-off-by:
Atish Patra <atish.patra@wdc.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
-
Atish Patra authored
Currently, the toolchains do not have support for hfence instruction. Hence, the instruction are hardcode until we have toolchain support. Signed-off-by:
Atish Patra <atish.patra@wdc.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
-
Atish Patra authored
This patch adds new IPI extension which replaces ipi related v0.1 extensions. This also adds a new API for ipi sending as trap handling is not necessary in v0.2 SBI IPI related extensions. It also modifies the IPI sending code which now accepts hart mask as a value instead of S-mode virtual address. Thus, the caller should set it to exact hart mask value everytime. Signed-off-by:
Atish Patra <atish.patra@wdc.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
-
Atish Patra authored
This patch adds support for TIME extension which replaces v0.1 timer extension. Signed-off-by:
Atish Patra <atish.patra@wdc.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
-
Atish Patra authored
We just need to distinguish only between FENCE and non FENCE related IPIs as all of the fence related requests are handled via fifo now. Remove the unnecessary IPI types related to individual fence types. Signed-off-by:
Atish Patra <atish.patra@wdc.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
-
Atish Patra authored
Take this opportunity to move the enums to macros as enums make sbi_ecall_interface.h unusable in assembly files. Signed-off-by:
Atish Patra <atish.patra@wdc.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
-
- Dec 16, 2019
-
-
Anup Patel authored
We should use MTINST CSR in misaligned load/store emulation whenever possible to avoid unpriv read in getting trapped instruction. This will improve preformance on HW having proper implementation of MTINST CSR. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com>
-
Anup Patel authored
The hypervisor v0.5 spec introduces two new CSRs for both M-mode and HS-mode which need to be considered when redirecting traps hence this patch. Signed-off-by:Anup Patel <anup.patel@wdc.com>
-
Anup Patel authored
We should treat load guest page fault in sbi_get_insn() as fetch guest patch fault. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com>
-
Anup Patel authored
We have two new trap CSRs namely mtval2 and mtinst when RISC-V hypervisor extension is available hence we extend struct sbi_trap_info accordingly. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com>
-
Anup Patel authored
As-per RISC-V hypervisor v0.5 spec, we have new guest page faults which need to be delegated to HS-mode. Also, we can have bits in in MIDELEG and MEDELEG hardwired to 1 which means we need to fix the sainty check on these CSRs at the end of delegate_traps() function. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com>
-
Anup Patel authored
With RISC-V H-extension v0.5 draft, we have special support for guest external interrupts so this patch adds related defines which were missed-out previously. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com>
-
- Dec 06, 2019
-
-
Martin Pietryka authored
GCC-9 will throw a warning when using the %s format specifier with a possible NULL parameter and since -Werror is used, the compilation breaks for GCC-9. In function 'sbi_boot_prints', inlined from 'init_coldboot' at <redacted>/opensbi/lib/sbi/sbi_init.c:107:3, inlined from 'sbi_init' at <redacted>/opensbi/lib/sbi/sbi_init.c:189:3: <redacted>/opensbi/lib/sbi/sbi_init.c:56:2: error: '%s' directive argument is null [-Werror=format-overflow=] 56 | sbi_printf("Platform Name : %s\n", sbi_platform_name(plat)); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors This is one way to fix this, currently there is nothing in the tree checking for `sbi_platfrom_name() == NULL` so we can just return "Unknown" instead of NULL on failure. Signed-off-by:Martin Pietryka <martin@pietryka.at> Reviewed-by:
Anup Patel <anup.patel@wdc.com> Tested-by:
David Abdurachmanov <david.abdurachmanov@sifive.com>
-
- Nov 27, 2019
-
-
Xiang W authored
Add assertions for misa_extension to prevent incoming illegal characters. Signed-off-by:
Xiang Wang <merle@hardenedlinux.org> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
-