Currently the process is terminated after the timeout. Add an option
to let the process resume after the timeout instead.

https://reviews.llvm.org/D138952

This was never updated for the address space number shuffle.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D139234

This adds some tablegen patterns for RSHRN, which performs a rounding
shift with narrow. This is similar to the existing SHRN patterns with an
extra addition to perform the rounding, that adds 1<<(shift-1) before
the right shift. Because the round immediate and the shift amount are
tied, it goes via a ComplexPattern that uses a SelectRoundingVLShr
method to perform the selection checks.

aarch64_neon_rshrn are expanded into the sequence of equivalent
instructions (trunc(shr(add(x, 1<<(sht-1)), sht))) so that they can be
converted back into RSHRN. Which also allows us to match raddhn through
the adjusted patterns that previously used aarch64_neon_rshrn.

DIfferential Revision: https://reviews.llvm.org/D140297

Specify python3, and replace / with // to do integer division.

attr-or-type-format.td contains tests for various attributes and types,
but nowhere in the testsuite is the customAssemblyFormat for an EnumAttr
(enum class in C++) exercised. Fix this by adding a test.

Signed-off-by: Ramkumar Ramachandra <r@artagnon.com>

Differential Revision: https://reviews.llvm.org/D140034

Ensure scalar is at least as wide as type, but only if the specified condition
is met.

Reviewed By: paquette

Differential Revision: https://reviews.llvm.org/D140305

The attiny4/attiny5/attiny9/attiny10 have a slightly modified
instruction set that drops a number of useful instructions. This patch
makes sure to not emit them on these "reduced tiny" cores.

The affected instructions are:

  * lds and sts (load/store directly from data)
  * ldd and std (load/store with displacement)
  * adiw and sbiw (add/sub register pairs)
  * various other instructions that were emitted without checking
    whether the chip actually supports them (movw, adiw, etc)

There is a variant on lds and sts on these chips, but it can only
address a limited portion of the address space and is mainly useful to
load/store I/O registers (as an extension to the in and out
instructions). I have not implemented it here, implementing it can be
done in a separate patch.

This patch is not optimal. I'm sure it can be improved a lot. For
example, we could teach the instruction selector to not select lddw/stdw
instructions so that the weird pointer adjustments are not necessary.
But for now I've focused just on correctness, not on code quality.

Updates: https://github.com/llvm/llvm-project/issues/53459

Differential Revision: https://reviews.llvm.org/D131867

D72845 implemented the equivalent IR optimization in InstCombine so it
seems that there's no advantage to doing it during isel too.

This partially reverts D72844.

Differential Revision: https://reviews.llvm.org/D140546

Differential Revision: https://reviews.llvm.org/D140535

C++17 defines the C11 `aligned_alloc`, so we can use that instead of
posix_memalign. This change allows building against picolibc without
defining _DEFAULT_SOURCE/_GNU_SOURCE.
The C11 `aligned_alloc` function should be available on all supported
non-Windows platforms except for macOS where we need version 10.15.

There is one caveat: aligned_alloc() requires that __size is a multiple of
__alignment, but [new.delete.general] only states "if the value of an
alignment argument passed to any of these functions is not a valid
alignment value, the behavior is undefined".
To handle calls such as ::operator new(1, std::align_val_t(128)), we
round up __size to __alignment (and check for wrap-around).
This is required at least for macOS where aligned_alloc(128, 1) returns
an error instead of allocating memory (glibc ignores the specification).

Differential Revision: https://reviews.llvm.org/D138196

There is a minor change in operand order (of a commutative
instruction).

The asm test has minor differences in instruction scheduling only.

The handling of return statements, added in support of context-sensitive
analysis, has a bug relating to functions that return reference
types. Specifically, interpretation of such functions can result in a crash from
a bad cast. This patch fixes the bug and guards all of that code with the
context-sensitive option, since there's no reason to execute at all when
context-sensitive analysis is off.

Differential Revision: https://reviews.llvm.org/D140430

This fixes an annoying assymmetry in the test organization. We have
known-never-nan.ll for dedicated isKnownNeverNaN handling tests, but
the isKnownNeverInfinity were in floating-point-compare.ll. Move the
more targeted tests into a separate file to match.

This didn't have a negative test.

Previously, the analysis modeled global variables appearing in the _body_ of
any function (including constructors). But, that misses those appearing in
constructor _initializers_. This patch adds the initializers to the set of
expressions used to determine which globals to model.

Differential Revision: https://reviews.llvm.org/D140501

Previously, in the case of an optional constructed from `nullopt`, we relied on
the value constructed for the `nullopt`. This complicates the implementation and
exposes it to bugs (indeed, one such was found), yet doesn't improve the
engine. Instead, this patch constructs a fresh optional representation, rather
than relying on the underlying nullopt representation.

Differential Revision: https://reviews.llvm.org/D140506

* Rewrite vector.transfer_write of vectors with 1 element to
  memref.store
* Rewrite vector.extract(vector.transfer_read) to memref.load

Differential Revision: https://reviews.llvm.org/D140391

I don't think the intent of this test is to make sure we only have one compile unit; it's to make sure request_compileUnits returns something sensible. Relax the test case to just make sure that the main source file is one of the compile units returned, even if there are others.

Fixes llvm.org/pr49418.

Reviewed By: labath

Differential Revision: https://reviews.llvm.org/D138344

The VFs and UFs may be more constrained as the plans are transformed
(e.g. see D135017 for an example).

To make sure the VFs/UFs included in the VPlan dump are accurate,
generate them when accessing a plan's name, rather than include them in
the name string set after initial construction.

The optimizer was folding the entire function to return 0. This
meant to be checking the character content of the pointer is the
string terminator, not null.

Also just make null inputs undefined. My docs for nanf say the
behavior of the argument is unspecified and segfaults on my system.