While simplifying some vector operators in DAG combine, we may need to
create new instructions for simplified vectors. At that time, we need to
make sure that all the flags of the new instruction are copied/modified
from the old instruction.

If "contract" is dropped from an instruction like FMUL, it may not
generate FMA instruction which would impact performance.

Here's an example where "contract" flag is dropped when FMUL is created.

Replacing.2 t42: v2f32 = fmul contract t41, t38
With: t48: v2f32 = fmul t38, t38

Co-authored-by: Sirish Pande <sirish.pande@amd.com>

Fold constructVariableDIEImpl into constructVariableDIE, simplify it and
group related functions.

Pull out the previously inline lambdas for visiting the active variant
of the DbgVariable to add location and related attributes as an overload
set for a private method
applyConcreteDbgVariableAttributes.

Rename applyVariableAttribute to reflect what kinds of attributes it
applies, and to contrast it with the new
applyConcreteDbgVariableAttributes.

Move constructLabelDIE down in the implementation file, so all of the
constructVariableDIE-related function impls are adjacent.

Reviewed By: guraypp

Differential Revision: https://reviews.llvm.org/D159535

This is the implementation of step 3 of

https://discourse.llvm.org/t/rfc-customizable-namespace-to-allow-testing-the-libc-when-the-system-libc-is-also-llvms-libc/73079.

Make add() function smart enough to understand that the shuffle of
a single entry is requested, if it sees that the second node is the same
as the first.

This patch updates the siginfo_t struct definition to match the
definition from the kernel here:

https://github.com/torvalds/linux/blob/master/include/uapi/asm-generic/siginfo.h

In particular, there are two main changes:

1. swap position of si_code and si_errno: si_code show come after
si_errno in all systems except MIPS. Since we don't MIPS, the order is
fixed for now, but can be easily \#ifdef'd if MIPS support is
implemented in the future.

2. We add a union of structs that are filled depending on the signal
raised.

This change was required for the fork and spawn integration tests in
rv32, since they fork/clone the running process, call
wait/waitid/waitpid, and read the status, which was wrong in rv32
because wait/waitid/waitpid are implemented in rv32 using SYS_waitid.

SYS_waitid takes a pointer to a siginfo_t and fills the proper fields in
the struct. The previous siginfo_t definition was being incorrectly
filled due to not taking into account the signal raised.

This `Block` member function introduced in
87d77d3c

 may be misleading to users as
the last operation in the block might have not been registered, so there
would be no way to ensure that is a terminator.

---------

Signed-off-by: Victor Perez <victor.perez@codeplay.com>

While there also remove some UB from the test.

Temporary workaround for the following CMake error:
```
CMake Error in /llvm/libcxx/benchmarks/CMakeLists.txt:
The compiler feature "cxx_std_23" is not known to CXX compiler
"IBMClang"
```

scalar.

No need to scan the whole graph when trying to find matching node for
the scalar, vectorized in several nodes, better to store corresponding
nodes along and scan just this small list.

Check the type of the phi node instead (as the comment already
indicates).

We can directly use the type of Offset here.

A lot of SCEV expressions only work on integers -- in which case
the effective type will always be the same as the type.

There is a lot more cleanup to do here.

I just fixed a bug in the core file equivalent where this was the issue.

This class avoids the issue by setting m_sve_state early but should
still be fixed so it doesn't crop up in a later refactor.

Flang was generating invalid IR when there was a GOTO to the body
of a DO loop. This happened because the value of step, computed at
the beginning of the loop, was being reused at the end of the loop,
that, for unstructured loops, is in another basic block. Because of
this, a GOTO could skip the beginning of the loop, that defined
step, and yet try to use it at the end of the loop, which is
invalid.

Instead of reusing the step value, it can be recomputed if it is a
constant, or stored and loaded to/from a temporary variable, for
non-constant step expressions.

Note that, while this change prevents the generation of invalid IR
on the presence of jumps to DO loop bodies, what happens if the
program reaches the end of a DO loop without ever passing through
its beginning is undefined behavior, as some control variables,
such as trip, will be uninitialized. It doesn't seem worth the
effort and overhead to ensure this legacy extension will behave
correctly in this case. This is consistent with at least gfortran,
that doesn't behave correctly if step is not equal to one.

Fixes: https://github.com/llvm/llvm-project/issues/65036

This reverts commit 3fa50358.

m_sve_state was not initialised which (I'm guessing) meant that
it could potentially be a value that matched a real SVE state.
Then we'd be acting as if we're streaming mode, for example,
without ever having the data required to back that up.

By sheer luck this only turn up on x86, AArch64 and ARM were fine.
It is UB regardless.

That commit introduced a trivial test breakage due to a bad rebase,
which this commit fixes.

[mlir][linalg][transform] Rename {masked_vectorize => vectorize => vectorize_children_and...}. (#66575)

This PR renames the vectorization transform ops as follows:

* `structured.masked_vectorize` => `structured.vectorize`. This reflects
the fact that since [recently](https://reviews.llvm.org/D157774) the op
can also handle the unmasked case.
* `structured.vectorize` =>
`structured.vectorize_children_and_applies_patterns`. This reflects the
fact that the op does not just vectorize the given payload op but all
vectorizable children contained in it, and applies patterns before and
after for preparation and clean-up.

This rename was discussed first
[here](https://reviews.llvm.org/D157774).

The PR also adapts and cleans ups the tablegen description of the
`VectorizeChildrenAndApplyPatternsOp` (formerly `VectorizeOp`).

This option has been superseded by the fixpoint verification
functionality.

expandCodeFor() was directly calling expandCodeForImpl(). Drop the
Impl variant.

Similar to #65598, if we're using a vslideup to insert a fixed length
vector into another vector, then we can work out the minimum number of
registers it will need to slide up across given the minimum VLEN, and
shrink the type operated on to reduce LMUL accordingly.

This is somewhat dependent on #66211 , since it introduces a subregister
copy that triggers a crash with -early-live-intervals in one of the
tests.

Stacked upon #66211

This reverts commit 43812c8c.

Due to failures on x86_64: https://lab.llvm.org/buildbot/#/builders/68/builds/60416

Derived-type-spec (such as `type(t)`) typically cause the instantiation
of a class which is also used to define the offsets of its data
components and the size of the class.

Fortran derived types are always "completely" defined (i.e., no
incomplete / opaque derived types exist on which we can build a pointer
to them like in C/C++) so they can have their offsets always computed.

However, we must be careful not to instantiate a derived type while it
is being defined. This can happen due to cycles introduced by forward
references, such as the one below.

```lang=fortran
  type t1
    type(t2), pointer :: b ! (A)
  end type t1

  type :: t2 ! (B)
    type(t1), pointer :: a ! (C)
  end type t2 ! (D)
```

At `(A)`, flang determines that this is a forward declaration so no
instantiation happens.

At `(B)`, flang determines `t2` is not a forward declaration anymore,
because we are defining it.

At `(C)`, flang chooses to instantiate `t1`. Instantiation ...

This reverts commit fb8f5915 and
b8e9450a.

Due to test suite failures on AArch64:
https://lab.llvm.org/buildbot/#/builders/183/builds/16057

Old iterator is invalidated upon SmallVector elements additions. Stores
index instead of iterator to avoid this.

Fixes https://github.com/llvm/llvm-project/issues/66938

PR: https://github.com/llvm/llvm-project/pull/66954

This adds the ability to read streaming SVE registers,
ZA, SVCR and SVG from core files.

Streaming SVE is in a new note NT_ARM_SSVE but otherwise
has the same format as SVE. So I've done the same as I
did for live processes and reused the existing SVE state
with an extra state for the mode variable.

ZA is in a note NT_ARM_ZA and again the handling matches
live processes. Except that it gets setup only once. A
disabled ZA reads as 0s as usual.

SVCR and SVG are pseudo registers, generated from the notes.

An important detail is that the notes represent what
you would have got if you read from ptrace at the time of
the crash.

This means that for a corefile in non-streaming mode,
there is still an NT_ARM_SSVE note and we check the header
flags to tell if it is active. We cannot just say if you
have the note you're in streaming mode.

The kernel does not provide register values for the inactive
mode and even if it did, they would be undefined, so if we find
st...

Check isSafeToExpand() before expanding the exit count. Otherwise
we may incorrectly speculate a udiv.

Fixes https://github.com/llvm/llvm-project/issues/66986.

The wide stream tests should be marked as `UNSUPPORTED: no-wide-characters`,
not XFAIL.

To get the bot back to green as we figure out how to handle piping data
into a test running behind a SSH executor.

In order to reduce noise for a MR.

Precommit test ahead of https://reviews.llvm.org/D159533 for ISD::FSHR /
AMDGPUISD::PERM combine

Noticed on D159533 and I've finally deal with the x86 regressions - MatchingStackOffset wasn't peeking through AssertZext nodes while trying to find CopyFromReg/Load sources, it was only removing them if they were part of a (trunc (assertzext x)) pattern.

Don't generate enums from the main VectorOps.td file as that
transitively includes enums from Arith.

---------

Co-authored-by: Nicolas Vasilache <ntv@google.com>

Support for SPIRV added, updated test SPV_INTEL_optnone.ll using the script.

Previously https://reviews.llvm.org/D157858