Without this gcc complains like
 ../lib/Target/X86/X86FixupVectorConstants.cpp:70:13: warning: unused variable 'CUndef' [-Wunused-variable]
    70 |   if (auto *CUndef = dyn_cast<UndefValue>(C))
       |             ^~~~~~

Remove the unused variable and change dyn_cast to isa.

The SimplifyClones pass relies on the assumption that the deallocOp
follows the cloneOp. However, a crash occurs when there is a
redundantDealloc preceding the cloneOp. This PR addresses the issue by
ensuring the presence of deallocOp after cloneOp. The verification is
performed by checking if the loop of the sub sequent node of cloneOp
reaches the tail of the list.

Fix #74306

The pattern rewriter documentation states that "*all* IR mutations [...]
are required to be performed via the `PatternRewriter`." This commit
adds two functions that were missing from the rewriter API:
`moveOpBefore` and `moveOpAfter`.

After an operation was moved, the `notifyOperationInserted` callback is
triggered. This allows listeners such as the greedy pattern rewrite
driver to react to IR changes.

This commit narrows the discrepancy between the kind of IR modification
that can be performed and the kind of IR modifications that can be
listened to.

The `.yml` file extension is a valid extension for the YAML files, but
it was not previously supported by the Clang Apply Replacements tool.
This commit adds support for processing `.yml` files. Without this
change, running the tool on a folder containing `.yml` files generated
by clang-tidy would have no effect.

Flags `-fveclib=name` were not passed to LTO flags.
This pass fixes that by converting the `-fveclib` flags to their
relevant names for opt's `-vector-lib=name` flags.

For example:
`-fveclib=SLEEF` would become `-vector-library=sleefgnuabi` and passed
through the `-plugin-opt` flag.

This pass should be the last machine function pass in pipeline, also
ignore `PI.runAfterPass(*P, MF, PassPA);` to avoid accessing a dangling
reference.

We convert existed macro fusions to TableGen.
    
Bacause `Fusion` depend on `Instruction` definitions which is defined
below `RISCVFeatures.td`, so we recommend user to add fusion features
when defining new processor.

`A` extension has been split into two parts: Zaamo (Atomic Memory
Operations) and Zalrsc (Load-Reserved/Store-Conditional). See also
https://github.com/riscv/riscv-zaamo-zalrsc.

This patch adds the MC support.

Reviewers: dtcxzyw, topperc, kito-cheng

Reviewed By: topperc

Pull Request: https://github.com/llvm/llvm-project/pull/78970

The pass was mistakenly identifying a fir.box_addr on a
fir.box/fir.class of a derived type with procedure pointer components as
being a fir.box_addr on a procedure.

Simply check if the input type is a fir.box_proc or function type (if
input already rewritten) and insert convert only in this case.

This caused "invalid fir.convert" internal error.

Without this gcc warned like
 ../lib/Target/AMDGPU/GCNDPPCombine.cpp:371: warning: unused variable 'OpSelOpr' [-Wunused-variable]
   371 |       if (auto *OpSelOpr =
       |
 ../lib/Target/AMDGPU/GCNDPPCombine.cpp:388: warning: unused variable 'OpSelHiOpr' [-Wunused-variable]
   388 |       if (auto *OpSelHiOpr =
       |

Remove the unused variables.

The #76150 fixed meaning of `transposeB` in NVVM dialect which was
initially implemented with opposite meaning.

This PR fixes the lowering of `nvgpu.warpgroup.mma` to NVVM dialect.

This will fix two integration tests:
gemm_f32_f16_f16_128x128x128.mlir
gemm_pred_f32_f16_f16_128x128x128.mlir

This fixes found non-determinism when `LLVM_REVERSE_ITERATION`
option is `ON`.

Fixes #79420.

Reviewers: ilovepi, MaskRay

Reviewed By: MaskRay

Pull Request: https://github.com/llvm/llvm-project/pull/79411

In the past PerformSplittingToNarrowingStores handled both int and float
ops, but since the introduction of MVETRUNC now only operates on float
operations, creating VCVTN nodes. It should be guarded by hasMVEFloatOps
to prevent a failure to select.

This reverts commit 0d0c2298.

Includes a bug fix for fcmp one handling, as well as for positive constants.

Here is the list of the renamed passes:
- `callbrprepare` -> `callbr-prepare`
- `dwarfehprepare` -> `dwarf-eh-prepare`
- `flattencfg` -> `flatten-cfg`
- `loweratomic` -> `lower-atomic`
- `lowerinvoke` -> `lower-invoke`
- `lowerswitch` -> `lower-switch`
- `winehprepare` -> `win-eh-prepare`
- `targetir` -> `target-ir`
- `targetlibinfo` -> `target-lib-info`

Legacy passes are not affected.

This is only valid on targets with architected SGPRs.

We now use PassT::name to distinguish Passes.

Indent line continuations by 2 spaces.
Drop -x c

These predicates can be used to represent `<`, `<=`, `>`, `>=`.

And a predicate for `in range` is added.

Change the return type of
 findScratchNonCalleeSaveRegister
to Register instead of unsigned.

Every place the function is called we already put the returned value in a
Register variable or compare it with another Register.

This fixes some gcc warnings:
 ../lib/Target/AArch64/AArch64FrameLowering.cpp:744: warning: enumeral and non-enumeral type in conditional expression [-Wextra]
   743 |     Register TargetReg = RealignmentPadding
       |     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   744 |                              ? findScratchNonCalleeSaveRegister(&MBB)
       |                              ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   745 |                              : AArch64::SP;
       |
 ../lib/Target/AArch64/AArch64FrameLowering.cpp:803: warning: enumeral and non-enumeral type in conditional expression [-Wextra]
   802 |     Register ScratchReg = RealignmentPadding
       |     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   803 |                               ? findScratchNonCalleeSaveRegister(&MBB)
       |                               ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   804 |                               : AArch64::SP;
       |

Previously, RISCVInsertReadWriteCSR inserted an FRM swap for any value
other than 7 and restored the original value right after the vector
instruction. This is inefficient if multiple vector instructions use the
same rounding mode if the next vector instruction uses a different
explicit rounding mode.

This patch implements a local optimization to solve the above problem.
We assume the starting rounding mode of the basic block is "dynamic."
When iterating through a basic block and encountering an instruction
whose rounding mode is not the same as the current rounding mode, we
change the current rounding mode and save the current rounding mode if
needed. And we may need to restore FRM when encountering function call,
inline asm and some uses of FRM.

The advanced version of this is to perform cross basic block analysis
for the starting rounding mode of each basic block.

This class is not specific to "Tr"(Transpose). It is
just for a normal load.

This patch is split off from #77342

- Correct for CodeSize cost that 1 instruction is not included. 3 is
from {VMV.S, ReductionOp, VMV.X}
- Add SplitCost
Unordered reduction chain a series of VADD/VFADD/... which scales with
LMUL.
 Ordered reductions chain a series of VFREDOSUMs.
- Use MVT to estimate VL.

Progress on https://github.com/openxla/iree/issues/16181

Promoted BMI instructions were supported in #73899

llvm-project/llvm/lib/Transforms/Instrumentation/MemProfiler.cpp:375:21:
 error: unused variable 'DL' [-Werror,-Wunused-variable]
  const DataLayout &DL = I->getModule()->getDataLayout();
                    ^
1 error generated.

As discussed in https://github.com/llvm/llvm-project/pull/79244, the
sized memory access callback is leftover stuff carried over from Asan,
can removed from the instrumentation.

Unlike ASan, MemProf uses the same memory access callback(inline
sequence) for different size memory access, remove unneeded TypeSize
stored in InterestingMemoryAccess.