- Sep 08, 2020
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Nikita Popov authored
These lambdas don't need copies, use const reference.
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Nikita Popov authored
For intrinsics supported by ConstantRange, compute the result range based on the argument ranges. We do this independently of whether some or all of the input ranges are full, as we can often still constrain the result in some way. Differential Revision: https://reviews.llvm.org/D87183
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Craig Topper authored
[SelectionDAG][X86][ARM] Teach ExpandIntRes_ABS to use sra+add+xor expansion when ADDCARRY is supported. Rather than using SELECT instructions, use SRA, UADDO/ADDCARRY and XORs to expand ABS. This is the multi-part version of the sequence we use in LegalizeDAG. It's also the same as the Custom sequence uses for i64 on 32-bit and i128 on 64-bit. So we can remove the X86 customization. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D87215
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Sanjay Patel authored
This was supposed to be an NFC cleanup, but there's a real logic difference (did not drop 'nsw') visible in some tests in addition to an efficiency improvement. This is because in the case where we have 2 GEPs, the code was *always* swapping the operands and negating the result. But if we have 2 GEPs, we should *never* need swapping/negation AFAICT. This is part of improving flags propagation noticed with PR47430.
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Sanjay Patel authored
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Craig Topper authored
[X86] Use the same sequence for i128 ISD::ABS on 64-bit targets as we use for i64 on 32-bit targets. Differential Revision: https://reviews.llvm.org/D87214
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Craig Topper authored
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Sanjay Patel authored
This is a follow-up suggested in D86420 - if we have a pair of stores in inverted order for the target endian, we can rotate the source bits into place. The "be_i64_to_i16_order" test shows a limitation of the current function (which might be avoided if we integrate this function with the other cases in mergeConsecutiveStores). In the earlier "be_i64_to_i16" test, we skip the first 2 stores because we do not match the full set as consecutive or rotate-able, but then we reach the last 2 stores and see that they are an inverted pair of 16-bit stores. The "be_i64_to_i16_order" test alters the program order of the stores, so we miss matching the sub-pattern. Differential Revision: https://reviews.llvm.org/D87112
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Eric Astor authored
MASM allows variables defined by equate statements to be used in expressions. Reviewed By: thakis Differential Revision: https://reviews.llvm.org/D86946
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Eric Astor authored
MASM aligns fields to the _minimum_ of the STRUCT alignment value and the size of the next field. Reviewed By: thakis Differential Revision: https://reviews.llvm.org/D86945
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Eric Astor authored
Add support for expressions of the form '1 or 2', etc. Reviewed By: thakis Differential Revision: https://reviews.llvm.org/D86944
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Simon Pilgrim authored
Already defined in includes.
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Simon Pilgrim authored
These are already defined in the CallingConvLower.h include.
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Simon Pilgrim authored
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Simon Pilgrim authored
Reduce to forward declarations and move includes to LeonPasses.cpp where necessary.
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Simon Pilgrim authored
The implementations no longer exist.
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Sanjay Patel authored
Check for no overflow along with an odd constant before we lose information by converting to bitwise logic. https://rise4fun.com/Alive/2Xl Pre: C1 != 0 %mx = mul nsw i8 %x, C1 %my = mul nsw i8 %y, C1 %r = icmp eq i8 %mx, %my => %r = icmp eq i8 %x, %y Name: nuw ne Pre: C1 != 0 %mx = mul nuw i8 %x, C1 %my = mul nuw i8 %y, C1 %r = icmp ne i8 %mx, %my => %r = icmp ne i8 %x, %y Name: odd ne Pre: C1 % 2 != 0 %mx = mul i8 %x, C1 %my = mul i8 %y, C1 %r = icmp ne i8 %mx, %my => %r = icmp ne i8 %x, %y
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Sanjay Patel authored
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alex-t authored
optimizeEndCF removes EXEC restoring instruction case this instruction is the only one except the branch to the single successor and that successor contains EXEC mask restoring instruction that was lowered from END_CF belonging to IF_ELSE. As a result of such optimization we get the basic block with the only one instruction that is a branch to the single successor. In case the control flow can reach such an empty block from S_CBRANCH_EXEZ/EXECNZ it might happen that spill/reload instructions that were inserted later by register allocator are placed under exec == 0 condition and never execute. Removing empty block solves the problem. This change require further work to re-implement LIS updates. Recently, LIS is always nullptr in this pass. To enable it we need another patch to fix many places across the codegen. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D86634
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Momchil Velikov authored
a warning about clobbering reserved registers (NFC). Also address some minor inefficiencies and style issues. Differential Revision: https://reviews.llvm.org/D86088
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- Sep 07, 2020
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Gabor Marton authored
We want the generice StdLibraryFunctionsChecker to report only if there are no specific checkers that would handle the argument constraint for a function. Note, the assumptions are still evaluated, even if the arguement constraint checker is set to not report. This means that the assumptions made in the generic StdLibraryFunctionsChecker should be an over-approximation of the assumptions made in the specific checkers. But most importantly, the assumptions should not contradict. Differential Revision: https://reviews.llvm.org/D87240
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Richard Barton authored
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Gabor Marton authored
Differential Revision: https://reviews.llvm.org/D84415
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Richard Barton authored
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Simon Pilgrim authored
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Simon Pilgrim authored
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Simon Pilgrim authored
We already simplify the unsigned comparisons if we've found the operands are non-negative, but we were still calling LowerVSETCCWithSUBUS which resulted in the PR47448 regressions.
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Simon Pilgrim authored
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Simon Pilgrim authored
Feed the Intrinsic::ID value directly instead of via the IsSigned/IsAddition bool flags.
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Sanjay Patel authored
Normal dead code elimination ignores assume intrinsics, so we fail to delete assumes that are not meaningful (and potentially worse if they cause conflicts with other assumptions). The motivating example in https://llvm.org/PR47416 suggests that we might have problems upstream from here (difference between C and C++), but this should be a cheap way to make sure we remove more dead code. Differential Revision: https://reviews.llvm.org/D87149
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Frederik Gossen authored
Merge the two lowering passes because they are not useful by themselves. The new pass lowers to `std` and `scf` is considered an auxiliary dialect. See also https://llvm.discourse.group/t/conversions-with-multiple-target-dialects/1541/12 Differential Revision: https://reviews.llvm.org/D86779
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Sjoerd Meijer authored
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Simon Pilgrim authored
Minor followup to D87101, we were expanding this to a neg+icmp+select pattern like we were in CGBuiltin
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Simon Pilgrim authored
[X86][SSE] Use llvm.abs.* vector intrinsics instead of old (deprecated) SSE/AVX intrinsics for combine tests This also allows us to extend testing to SSE2+ targets
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Alex Zinenko authored
This was likely overlooked when ValueRange was first introduced. There is no reason why StructuredIndexed needs specifically an ArrayRef so use ValueRange for better type compatibility with the rest of the APIs. Reviewed By: nicolasvasilache, mehdi_amini Differential Revision: https://reviews.llvm.org/D87127
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Esme-Yi authored
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Georgii Rymar authored
LLVM style code can be simplified to avoid the duplication of logic related to printing dynamic relocations. Differential revision: https://reviews.llvm.org/D87089
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Daniel Muñoz authored
Add PRIVATE keyword in target_link_libraries to prevent CMake Error on Windows. While trying to compile llvm/clang on Windows, the following CMake error occurred. The reason is a missing PUBLIC/PRIVATE/INTERFACE keyword in target_link_libraries. ` CMake Error at utils/KillTheDoctor/CMakeLists.txt:5 (target_link_libraries): The keyword signature for target_link_libraries has already been used with the target "KillTheDoctor". All uses of target_link_libraries with a target must be either all-keyword or all-plain. The uses of the keyword signature are here: * cmake/modules/AddLLVM.cmake:771 (target_link_libraries) ` Reviewed By: tambre Differential Revision: https://reviews.llvm.org/D87203
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Simon Pilgrim authored
These have been auto upgraded for some time so this is just a tidyup.
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Simon Pilgrim authored
We're now getting close to having the necessary analysis/combines etc. for the new generic llvm.abs.* intrinsics. This patch updates the SSE/AVX ABS vector intrinsics to emit the generic equivalents instead of the icmp+sub+select code pattern. Differential Revision: https://reviews.llvm.org/D87101
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