MVE has a basic symmetry between it's normal loads/store operations and
the masked variants. This means that masked loads and stores can use
pre-inc and post-inc addressing modes, just like the standard loads and
stores already do.

To enable that, this patch adds all the relevant infrastructure for
treating masked loads/stores addressing modes in the same way as normal
loads/stores.

This involves:
- Adding an AddressingMode to MaskedLoadStoreSDNode, along with an extra
   Offset operand that is added after the PtrBase.
- Extending the IndexedModeActions from 8bits to 16bits to store the
   legality of masked operations as well as normal ones. This array is
   fairly small, so doubling the size still won't make it very large.
   Offset masked loads can then be controlled with
   setIndexedMaskedLoadAction, similar to standard loads.
- The same methods that combine to indexed loads, such as
   CombineToPostIndexedLoadStore, are adjusted to handle masked loads in
   the same way.
- The ARM backend is then adjusted to make use of these indexed masked
   loads/stores.
- The X86 backend is adjusted to hopefully be no functional changes.

Differential Revision: https://reviews.llvm.org/D70176

DIExpressions with shift operators should not be fragmented for the same
reason as arithmetic operators: carry over cannot be expressed from one
fragment to the other, so an invalid result would be produced.

Differential Revision: https://reviews.llvm.org/D70601

This is a follow up commit to address post-commit comment in D70443

Differential revision: https://reviews.llvm.org/D70443

Differential revision: https://reviews.llvm.org/D70405

Need to perform the instantiation of the combiner/initializer even if
the resulting type is not dependent, if the construct is defined in
templates in some cases.

Actually, just testing GitHub commit rights.

Summary: Adds support for softening FCOPYSIGN operands.
Adds RISC-V tests that exercise the new softening code.

Reviewers: asb, lenary, efriedma
Reviewed By: efriedma
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70679

Summary: Adds tablegen patterns to explicitly handle fcopysign where the
magnitude and sign arguments have different types, due to the sign value casts
being removed the by DAGCombiner. Support for RV32IF follows in a separate
commit. Adds tests for all relevant scenarios except RV32IF.

Reviewers: lenary
Reviewed By: lenary
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70678

Currently we have following issues:
1) We have 2 different implementations with a different behaviors for GNU/LLVM styles.
2) Errors are either not handled at all or we call report_fatal_error with not helpfull messages.
3) There is no test coverage even for those errors that are reported.

This patch reimplements parsing of the SHT_GNU_verdef section entries
in a single place, adds a few error messages and test coverage.

Differential revision: https://reviews.llvm.org/D70495

This quashes a -Wformat-truncation warning.

Pulling a couple of extra tests out of
D64258
before abandoning in favor of
D70714

Crushing a "sprintf" buffer is null warning.

It removes 2 precompiled binaries used which are now
can be crafted with the use of yaml2obj.

Differential revision: https://reviews.llvm.org/D70711

But do not enable it under -Wextra until libcxx issue is solved.

Summary:
I recently re-discovered that the unsinged stream operators of the
lldb_private::Stream class have a surprising behavior in that they print
the number in hex. This is all the more confusing because the "signed"
versions of those operators behave normally.

Now that, thanks to Raphael, each Stream class has a llvm::raw_ostream
wrapper, I think we should delete most of our formatting capabilities
and just delegate to that. This patch tests the water by just deleting
the operators with the most surprising behavior.

Most of the code using these operators was printing user_id_t values. It
wasn't fully consistent about prefixing them with "0x", but I've tried
to consistenly print it without that prefix, to make it more obviously
different from pointer values.

Reviewers: teemperor, JDevlieghere, jdoerfert

Subscribers: lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D70241

Include the fancier DWARF5 sections too.

[yaml2obj] - Fix BB after «[yaml2obj] - Teach tool to describe SHT_GNU_verdef section with a "Content" property.»

Fixed a temporary file name.

BB: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-ubuntu/builds/669

This way it looks more like the code around it. The assert is also gone as it just
checks that the variables we declare directly above were not initialized by anyone.
That made more sense when this was one large function.

Part of the work to split up this monolithic parsing function.

Summary:
We used to scan the code everytime when computing the LSP position to the offset
(respect the LSP encoding). Now we only scan the source code once.

Reviewers: ilya-biryukov

Subscribers: MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D70441

As discussed offline, something different from `EXPECT_EQ` should be
used to check if the container contains enough items before accessing
them so that other tests can still be run even if the assertion fails as
opposed to having `EXPECT_EQ` failing and then aborting the run due to
the errors caused by out-of-bounds memory access.

Reviewed by: ilya-biryukov

Differential Revision: https://reviews.llvm.org/D70528

There is no way to set raw content for SHT_GNU_verdef section.
This patch implements it.

Differential revision: https://reviews.llvm.org/D70710

Patch by raj.khem (Khem Raj)

Differential Revision: https://reviews.llvm.org/D68543

Fix for PR24072:

X86 instructions jrcxz/jecxz/jcxz performs short jumps if rcx/ecx/cx register is 0
The maximum relative offset for a forward short jump is 127 Bytes (0x7F).
The maximum relative offset for a backward short jump is 128 Bytes (0x80).

Gnu assembler warns when the distance of the jump exceeds the maximum but llvm-as does not.

Patch by Konstantin Belochapka and Alexey Lapshin

Differential Revision: https://reviews.llvm.org/D70652

Part of the work to split up this monolithic parsing function.

Part of the work to split up this monolithic parsing function.

Should be NFC but due to the kafkaesque control flow in this case statement this might
have some unintended side effects.

Part of the work to split up this monolithic parsing function.

Add the work-group and miscellaneous vector builtin functions from the
OpenCL C specification.

Patch by Pierre Gondois and Sven van Haastregt.

Summary:
Adds intrinsics for the following:
  - fcvt
  - fcvtzs & fcvtzu
  - scvtf & ucvtf
  - fcvtlt, fcvtnt
  - fcvtx & fcvtxnt

Reviewers: huntergr, sdesmalen, dancgr, mgudim, efriedma

Reviewed By: sdesmalen

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cameron.mcinally, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70180

Add some more helper functions to ReachingDefs to query the uses of
a given MachineInstr and also to query whether two MachineInstrs use
the same def of a register.

For Arm, while tail-predicating, these helpers are used in the
low-overhead loops to remove the dead code that calculates the number
of loop iterations.

Differential Revision: https://reviews.llvm.org/D70240

The improvement in the machine verifier for operand types (D63973) discovered
a bad operand in a test using a PPA instruction. It was an immediate 0 where
a register was expected.

This patch fixes this (NFC) by now making the PPA second register operand
NoRegister instead of a zero immediate in the MIR.

Review: Ulrich Weigand
https://reviews.llvm.org/D70501

Add several new methods to ReachingDefAnalysis:
- getReachingMIDef, instead of returning an integer, return the
  MachineInstr that produces the def.
- getInstFromId, return a MachineInstr for which the given integer
  corresponds to.
- hasSameReachingDef, return whether two MachineInstr use the same
  def of a register.
- isRegUsedAfter, return whether a register is used after a given
  MachineInstr.

These methods have been used in ARMLowOverhead to replace searching
for uses/defs.

Differential Revision: https://reviews.llvm.org/D70009

Part of the work to split up this monolithic parsing function.