[UpdateTestChecks] Prevent rapid onset insanity when forced to write LoopVectorize-driven costmodel tests

Subj, or on other words, we have a lot of tests that are driven by
the LoopVectorizer's debug output, but we don't have
any meaningful way to autogenerate checklines in them,
which means that an insurmountable amount of manual work
is required when modifying the appropriate cost models.

That is not sustainable, so this presents a solution.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D121133

Reviewed By: Mordante, var-const, #libc

Spies: sstefan1, libcxx-commits, mgorny

Differential Revision: https://reviews.llvm.org/D122982

Similar to D122281, we should firstly exclude all scalable vector extending
stores and then selectively enable those which we directly support.

Also merge integer and float scalable vector into scalable_vector_valuetypes.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D123449

Before that change, constant-size `bcmp` would miss an opportunity to generate
a more efficient equality pattern and would generate a -1/0-1 pattern
instead.

Differential Revision: https://reviews.llvm.org/D123849

IAS has been enabled on WebAssembly since commit 0a55d3f5.

This patch makes possible generating NVPTX assembly check lines with
update_llc_test_checks.py utility.

Differential Revision: https://reviews.llvm.org/D122986

Reviewed By: MaskRay, jpienaar

Differential Revision: https://reviews.llvm.org/D123836

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D123274

Similar to D123750 for AArch64.

Test the behavior when a MUL is used multiple times, as well as when it
is uniform.

Run the tests for gfx9 as well, which added S_MUL_HI_[IU]32.

In order to increase parallism, certain ops with regions and have the
IsIsolatedFromAbove trait will have their verification delayed. That
means the region verifier may access the invalid ops and may lead to a
crash.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D122771

There's a missed opportunity here that a later patch will exploit.

When formatted input (not list-directed or NAMELIST) is in "BZ" mode,
either because a BZ control edit descriptor appeared in a FORMAT or
BLANK="ZERO" appeared in OPEN or READ, input editing must not skip
over blanks before or within the input field.

Differential Revision: https://reviews.llvm.org/D123725

Integer materializing can generate LU12I_W, ORI, LU32I_D, LU52I_D and
ADDI_W instructions.

According to the sign-extended behavior of these instructions
(except ORI), the generated instruction sequence can be improved.

For example, load -1 into general register:
The ADDI_W instruction performs the operation that the [31:0] bit data
in the general register `rj` plus the 12-bit immediate `simm12` sign
extension 32-bit data; the resultant [31:0] bit is sign extension, then
written into the general register `rd`.

Normal sequence:

```
lu12i.w $a0, -1
ori $a0, $a0, 2048
```

Improved with sign-extended instruction:

```
addi.w $a0, $zero,  -1
```

Reviewed By: SixWeining, MaskRay

Differential Revision: https://reviews.llvm.org/D123290

Add vector op warp_execute_on_lane_0 that will be used to do incremental
vector distribution in order to target warp level vector programming for
architectures with GPU-like SIMT programming model.
The idea behing the op is discussed further on discourse:
https://discourse.llvm.org/t/vector-vector-distribution-large-vector-to-small-vector/1983/23

Differential Revision: https://reviews.llvm.org/D123703

This would have assert before during tensor type construction with
opaque error, assert and fail earlier now.

Differential Revision: https://reviews.llvm.org/D123579

Remove duplicate version string identification

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D123549

This revision adds vector predication select, merge and load/store intrinsic ops.

Differential Revision: https://reviews.llvm.org/D123477

The HIP headers want to use this to swap the implementation of the
function, rather than relying on backend expansion of the generic
atomic instruction.

Fixes: SWDEV-332998

This enables no combines, just adds the boilerplate for the new pass.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D123795

This didn't work at all before, and would assert on any frame
index. Also copy the other fields, which I believe should cover
everything. There are a few that are untested since MIR serialization
is apparently still missing them (isStatepointSpillSlot,
ObjectSSPLayout, and ObjectSExt/ObjectZExt).

To avoid clashing with names of user derived types, the redundant
syntax TYPE(intrinsic type spec) must be interpreted as a monomorphic
derived type when "intrinsic type spec" is a single word.  This
affects TYPE(BYTE) and TYPE(DOUBLECOMPLEX), but not TYPE(DOUBLE COMPLEX)
in free form source.

Differential Revision: https://reviews.llvm.org/D123724

Fixed hostcall offset check to compare against kernarg segment size
and implicit arguments. Improved the corresponding debug print.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D123827