- Apr 01, 2021
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George Mitenkov authored
When folding addo/subo with undef, the current convention is to use { -1, false } for addo and { 0, false } for subo. This was fixed for InstSimplify in https://reviews.llvm.org/rGf094d65beaa492e845b03561eddd75b5be653a01, but not in ConstantFolding. Reviewed By: nikic, lebedev.ri Differential Revision: https://reviews.llvm.org/D99564 -
Alexey Bataev authored
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peter klausler authored
f18 was emitting a bogus error message about the lack of a TARGET attribute when a pointer was initialized with a component of a variable that was a legitimate TARGET. Differential Revision: https://reviews.llvm.org/D99665
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Huihui Zhang authored
Use SetVector instead of SmallPtrSet to track values with uniform use. Doing this can help avoid non-determinism caused by iterating over unordered containers. This bug was found with reverse iteration turning on, --extra-llvm-cmake-variables="-DLLVM_REVERSE_ITERATION=ON". Failing LLVM test consecutive-ptr-uniforms.ll . Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D99549
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Suraj Sudhir authored
Reviewed By: stellaraccident Differential Revision: https://reviews.llvm.org/D99628
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Petr Hosek authored
This helper method is useful even outside of Gnu toolchains, so move it to ToolChain so it can be reused in other toolchains such as Fuchsia. Differential Revision: https://reviews.llvm.org/D88452
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Thomas Lively authored
Removes the prototype builtin and intrinsic for i64x2.eq and implements that instruction as well as the other i64x2 comparison instructions in the final SIMD spec. Unsigned comparisons were not included in the final spec, so they still need to be scalarized via a custom lowering. Differential Revision: https://reviews.llvm.org/D99623
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Juneyoung Lee authored
This is a patch teaching ValueTracking that `s/u*.with.overflow` intrinsics do not create undef/poison and they propagate poison. I couldn't write a nice example like the one with ctpop; ValueTrackingTest.cpp were simply updated to check these instead. This patch helps reducing regression while fixing https://llvm.org/pr49688 . Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D99671
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Philip Reames authored
This fixes an issue introduced with my change d4648e, and reported in pr49768. The root problem is that dominance collapses in unreachable code, and that LoopInfo explicitly only models reachable code. Since the recurrence matcher doesn't filter by reachability (and can't easily because not all consumers have domtree), we need to bailout before assuming that finding a recurrence implies we found a loop.
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Craig Topper authored
The default expansion creates a MUL and either a MULHS/MULHU. Each of those separately expand to sequences that use one or more PMULLW instructions as well as additional instructions to extend the types to vXi16. The MULHS/MULHU expansion computes the whole 16-bit product, but only keeps the high part. We can improve the lowering of SMULO/UMULO for some cases by using the MULHS/MULHU expansion, but keep both the high and low parts. And we can use those parts to calculate the overflow. For AVX512 we might have vXi1 overflow outputs. We can improve those by using vpcmpeqw to produce a k register if AVX512BW is enabled. This is a little better than truncating the high result to use vpcmpeqb. If we don't have avx512bw we can extend up to v16i32 to use vpcmpeqd to produce a k register. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97624
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Shimin Cui authored
On ppc64 linux , MachineLICM will hoist caller preserved registers, including TOC loads of the global variable address, out of loops. This is to enable this on AIX for both ppc64 and ppc32. Differential Revision: https://reviews.llvm.org/D99076
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Craig Topper authored
We previously couldn't optimize out a TEST if the branch/setcc/cmov used the overflow flag. This patches allows the TEST to be removed if the flag producing instruction is known to clear the OF flag. Thats what the TEST instruction would have done so that should be equivalent. Need to add test cases. I'll try to get back to this if I have bandwidth. Fixes PR48768. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D94856
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Wael Yehia authored
in this patch we add a new libLTO API to specify debug options independent of an lto_code_gen_t. This allows clients to pass codegen flags (through libLTO) which otherwise today are ignored. Reviewed By: steven_wu Differential Revision: https://reviews.llvm.org/D92611
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Craig Topper authored
Our CLZW isel pattern is quite easily broken by surrounding code preventing it from matching sometimes. This usually results in failing to remove the and X, 0xffffffff inserted by type legalization. The add with -32 that type legalization also inserts will often gets combined into other add/sub nodes. That doesn't usually result in extra code when we don't use clzw. CTTZ seems to be less fragile, but I wanted to keep it consistent with CTLZ. Reviewed By: asb, HsiangKai Differential Revision: https://reviews.llvm.org/D99317
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Jay Foad authored
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Jay Foad authored
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Craig Topper authored
[RISCV] Add isel patterns to select vsub_vx intrinsic to vadd.vi if it uses a small enough immediate Also modify the simm5_plus1 check because Imm-1 is UB if Imm happens to be INT64_MIN. I don't think the compiler would optimize based on that in this usage, but it could fail UBSan or -ftrapv. Reviewed By: HsiangKai, frasercrmck Differential Revision: https://reviews.llvm.org/D99637
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Arthur Eubanks authored
Reviewed By: sgraenitz Differential Revision: https://reviews.llvm.org/D99604
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Heejin Ahn authored
D99627 fixed a decoding bug, not an encoding bug. This renames the test to correct it and fix comments. Reviewed By: dschuff Differential Revision: https://reviews.llvm.org/D99644
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- Mar 31, 2021
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Sanjay Patel authored
This is a missing optimization based on an example in: https://llvm.org/PR49763 As noted there and the test here, we could add a more general fold if that is shown useful. https://alive2.llvm.org/ce/z/xEHdTv https://alive2.llvm.org/ce/z/97dcY5
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Sanjay Patel authored
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Bradley Smith authored
Differential Revision: https://reviews.llvm.org/D99265
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Timm Bäder authored
... instantiations They are currently not being diagnosed because ProhibitAttributes() does not handle attribute lists with an invalid source range. But once it does, we need to allow GNU attributes in this place. Additionally, start optionally diagnosing empty attr lists in ProhibitCXX11Attributes(), since ProhibitAttribute() does it. Differential Revision: https://reviews.llvm.org/D97362
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Arthur O'Dwyer authored
Because the constexpr-time codepath triggers a Clang bug. It seems that Clang compiles it okay in release mode, but when Clang itself is compiled in debug mode (with assertions turned on), this input triggers an assertion failure in Clang itself. See comments on D96385 and Clang bug report https://bugs.llvm.org/show_bug.cgi?id=45879 This commit should get the debug-mode buildbots back to green.
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Luís Marques authored
See D80668, rG7b483264 and https://bugs.llvm.org/show_bug.cgi?id=46117 for details of the issue. Differential Revision: https://reviews.llvm.org/D99108
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Sander de Smalen authored
This marks FSIN and other operations to EXPAND for scalable vectors, so that they are not assumed to be legal by the cost-model. Depends on D97470 Reviewed By: dmgreen, paulwalker-arm Differential Revision: https://reviews.llvm.org/D97471
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Sander de Smalen authored
Let getIntrinsicInstrCost call getTypeBasedIntrinsicInstrCost for scalable vectors, similar to how this is done for fixed-width vectors, instead of falling back on BaseT::getIntrinsicInstrCost(). If the intrinsic cannot be costed (or is not overloaded by the target), it will return InstructionCost::getInvalid() instead. Depends on D97469 Reviewed By: david-arm Differential Revision: https://reviews.llvm.org/D97470
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Anton Bikineev authored
This adds support for C++2b's z/uz suffixes for size_t literals (P0330).
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Joerg Sonnenberger authored
The standard guarantees sleep durations of 2^63-1 nanoseconds to work. Instead of depending on INT64_MAX or ULONGLONG_MAX to exist via the header pollution, fold the constant directly. That has the additional positive side effect that it avoids long double arithmetic bugs in GCC. Differential Revision: https://reviews.llvm.org/D99516
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Balázs Kéri authored
This reverts commit 49c0ab6d. Test failures showed up because non-deterministic output.
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Sander de Smalen authored
This patch migrates the TTI cost interfaces to return an InstructionCost. See this patch for the introduction of the type: https://reviews.llvm.org/D91174 See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2020-November/146408.html Depends on D97468 Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D97469
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Sander de Smalen authored
This patch migrates the TTI cost interfaces to return an InstructionCost. See this patch for the introduction of the type: https://reviews.llvm.org/D91174 See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2020-November/146408.html Depends on D97466 Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D97468
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Max Kazantsev authored
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Muhammad Omair Javaid authored
This reverts commit 1164b4e2. Reason: LLDB AArch64 Linux buildbot failure
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Muhammad Omair Javaid authored
This reverts commit 9ab67718. Reason: LLDB AArch64/Linux buildbot failure.
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Liqiang Tao authored
Attempts to compute savings more accurately cannot impact the set of critically important call sites. Reviewed By: kazu Differential Revision: https://reviews.llvm.org/D98577
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Roman Lebedev authored
This is an improvement over Zen 2, where only branch fusion is supported, as per Agner, 21.4 Instruction fusion. AMD SOG 17h has no mention of fusion. AMD SOG 19h, 2.9.3 Branch Fusion The following flag writing instructions support branch fusion with their reg/reg, reg/imm and reg/mem forms * CMP * TEST * SUB * ADD * INC (no fusion with branches dependent on CF) * DEC (no fusion with branches dependent on CF) * OR * AND * XOR Agner, 22.4 Instruction fusion <...> This applies to CMP, TEST, ADD, SUB, AND, OR, XOR, INC, DEC and all conditional jumps, except if the arithmetic or logic instruction has a rip-relative address or both an address displacement and an immediate operand.
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Balazs Benics authored
D99576 introduced a duplicate symbol, now im removing it. Differential Revision: https://reviews.llvm.org/D99576
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Fraser Cormack authored
This adds almost everything required for supporting the new stepvector intrinsic on RVV. It is lowered to the existing VID_VL SDNode. The only exception is a limitation that RV32 cannot yet lower the intrinsic on i64 vectors. This is because the step operand is (currently) required to be at least as large as the vector element type. I will look into patching that out and loosening the requirement to only an integer pointer type. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D99594
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Muhammad Omair Javaid authored
This reverts commit 73cf85e5.
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