…9c849f42cf

This patch is based on a previous PR https://reviews.llvm.org/D144657
that added alloca address space handling to MLIR's DataLayout and DLTI
interface. This patch aims to add identical features to import and
access the global and program memory space through MLIR's
DataLayout/DLTI system.

[Flang][Driver] Enable gpulibc/nogpulibc options for Flang, which allows linking of GPU LIBC for the fortran and OpenMP runtime (#77135)

This patch seeks to add the -gpulibc and -nogpulibc for Flang, which
allows the linking of the GPU libc library, this allows the use of
memcpy and other useful library functions for GPU.

In particular, this allows the Fortran runtime (written in C++) to be
compiled for offload and then linked against the GPU LIBC library via
this option to resolve memcpy and other C library functions that the
fortran runtime depends on for AMD GPU devices (and likely other GPU
devices).

This is the current method I've tested and found to be able to utilise
the Fortran runtime when compiled for AMD GPU, albeit it requires
compiling libc for GPU and then the Fortran runtime for GPU, so not
particularly straight forward or user friendly yet.

Activating this option will allow the subset of C functions to also be
utilised for GPU in other C/C++ based Fortran libraries if any are made
when linking against GPU libc.

This patch fixes the crash issue in the test:
CodeGen/LoongArch/can-not-realign-stack.ll

Register allocator may spill virtual registers to the stack, which    
introduces stack alignment requirements (when the size of spilled     
    registers exceeds the default alignment size of the stack). If a  
function does not have stack alignment requirements before register   
allocation, registers used for stack alignment will not be preserved. 

Therefore, we should implement `canRealignStack()` to inform the      
register allocator whether it is allowed to perform stack realignment 
operations.

This test will crash with expensive check.

Crash message:
```
*** Bad machine code: Using an undefined physical register ***
- function:    main
- basic block: %bb.0 entry (0x20fee70)
- instruction: $r3 = frame-destroy ADDI_D $r22, -288
- operand 1:   $r22
```

This follows on from #76708, allowing
`cast<ConstantSDNode>(N)->getZExtValue()` to be replaced with just
`N->getAsZextVal();`
    
Introduced via `git grep -l "cast<ConstantSDNode>\(.*\).*getZExtValue" |
xargs sed -E -i
's/cast<ConstantSDNode>\((.*)\)->getZExtValue/\1->getAsZExtVal/'` and
then using `git clang-format` on the result.

These operations has been available for a while, but were not described
in the tutorial. Add a new chapter on using and defining match
operations.

Introduce a new match combinator into the transform dialect. This
operation collects all operations that are yielded by a satisfactory
match into its results. This is a simpler version of `foreach_match`
that can be inserted directly into existing transform scripts.

Update AMDGPU CodeGen lit tests to check for COV5 ABI.

Reland #77054.

- Add EmitC passes into Pass.md
- Modify header level of the pass description to under the
`LegalizeVectorStorage` pass

Since Knight Landing and Knight Mill microarchitectures are EOL, we
would like to remove intrinsic supports for its specific ISA in LLVM 19.
In LLVM 18, we will first emit a warning for the usage.

We have added a new pass that looks for loops such as the following:

```
  while (i != max_len)
      if (a[i] != b[i])
          break;

  ... use index i ...
```

Although similar to a memcmp, this is slightly different because instead
of returning the difference between the values of the first non-matching
pair of bytes, it returns the index of the first mismatch. As such, we
are not able to lower this to a memcmp call.

The new pass can now spot such idioms and transform them into a
specialised predicated loop that gives a significant performance
improvement for AArch64. It is intended as a stop-gap solution until
this can be handled by the vectoriser, which doesn't currently deal with
early exits.

This specialised loop makes use of a generic intrinsic that counts the
trailing zero elements in a predicate vector. This was added in
https://reviews.llvm.org/D159283 and for SVE we end up with brkb & incp
instr...

fir::isPolymorphic was returning false for TYPE(*) assumed-size arrays
causing bad fir.rebox to be created when passing a polymorphic actual
argument to such TYPE(*) dummy.

Fix fir::isAssumedSize to return true for fir.ref<fir.array<none>> and
fir.ref<none>.

@cabreraam, I found this bug when testing your patch, although it is not
caused by it, so you may hit it when passing TYPE(*) deferred shape of
to assumed size TYPE(*) with a different rank.

llvm-project/llvm/include/llvm/CodeGen/StackProtector.h:69:10:
error: class 'AnalysisInfoMixin' was previously declared as a struct; this is valid, but may result in linker errors under the Microsoft C++ ABI [-Werror,-Wmismatched-tags]
   69 |   friend class AnalysisInfoMixin<SSPLayoutAnalysis>;
      |          ^
llvm-project/llvm/include/llvm/IR/PassManager.h:414:8: note: previous use is here
  414 | struct AnalysisInfoMixin : PassInfoMixin<DerivedT> {
      |        ^
llvm-project/llvm/include/llvm/CodeGen/StackProtector.h:69:10: note: did you mean struct here?
   69 |   friend class AnalysisInfoMixin<SSPLayoutAnalysis>;
      |          ^~~~~
      |          struct
1 error generated.

The original `StackProtector` is both transform and analysis pass, break
it into two passes now. `getAnalysis<StackProtector>()` could be now
replaced by `FAM.getResult<SSPLayoutAnalysis>(F)` in new pass system.

https://github.com/llvm/llvm-project/issues/75424 

Add Coprocessor Instrinsics

Fix test failures after auto-merge of f9fec402

This patch updates `cxx_dr_status.html` to bring it in sync with Core Issues List Revision 113.

At the moment, block and edge masks are created on demand, which means
that they are inserted at the point where they are demanded and then
cached. It is possible that the mask for a block is looked up later at a
point that's not dominated by the point where the mask has been
inserted.

To avoid this, create masks up front on entry to the corresponding basic
block and leave it to VPlan simplification to remove unneeded masks.

Note that we need to create masks for all blocks, if any of the blocks
in the loop needs predication, as computing the mask of a block depends
on the masks of its predecessor.

Needed for #76090.

https://github.com/llvm/llvm-project/pull/76635

When there is just one element in the type equivalence class (TEC),
`inferNamedOperandType` fails because it does not consider the passed
operand as a suitable one. This is incorrect when inferring the type of
an (unnamed) immediate operand.

`*OpsIncGen` should depend only on the respective `*OpsTdFiles`.

In practice maybeAtomic = 0 is used to prevent SIMemoryLegalizer from
interfering with instructions that are mayLoad or mayStore but lack
MachineMemOperands. These instructions should be the exception not the
rule, so this patch sets maybeAtomic = 1 by default and only overrides
it to 0 where necessary.

Depends #76678

Mark instance variable offset symbols with `dllexport`/`dllimport` if
they are not hidden and the interface declaration is marked with
`dllexport`/`dllimport`, when using the GNUstep 2.x ABI.

/cc @davidchisnall

Requested in https://github.com/llvm/llvm-project/pull/77078, I agree
that we may as well be unambiguous.

GFX12 has separate wait instructions per counter e.g. S_WAIT_LOADCNT.
S_WAITCNT still exists but is deprecated and codegen should stop using
it. S_WAITCNT_* (e.g. S_WAITCNT_VSCNT) are removed.

This patch adds/removes MC layer support for these instructions.

This adds MLIR versions of the Arm streaming vector length intrinsics.
These allow reading the streaming vector length regardless of the
streaming mode.

toFeatures and toFeatureVector both output a list of target feature
flags, just with a slightly different interface. toFeatures keeps any
unsupported extensions, and also provides a way to append negative
extensions (AddAllExtensions=true).

This patch combines them into one function, so that a later patch will
be be able to get a std::vector of features that includes all the
negative extensions, which was previously only possible through the
StrAlloc interface.

[DWARFLinker][DWARFLinkerParallel][NFC] Refactor DWARFLinker&DWARFLinkerParallel to have a common library. Part 1. (#75925)

This patch creates DWARFLinkerBase library, places DWARFLinker code into
DWARFLinker\Classic, places DWARFLinkerParallel into DWARFLinker\Parallel.
updates BOLT to use new library. This patch is NFC.

This is done using libquadmath and the mappings are only available if
libquadmath was found by cmake.
Support for non quad bessels is already available on POSIX platform
using libm extensions.

When initializing a union that constrain a struct with a flexible array
member, and the initializer list is empty, we currently trigger an
assertion failure. This happens because getFlexibleArrayInitChars()
assumes that the initializer list is non-empty.

Fixes https://github.com/llvm/llvm-project/issues/77085.