These predicates can be used to represent `<`, `<=`, `>`, `>=`.

And a predicate for `in range` is added.

Change the return type of
 findScratchNonCalleeSaveRegister
to Register instead of unsigned.

Every place the function is called we already put the returned value in a
Register variable or compare it with another Register.

This fixes some gcc warnings:
 ../lib/Target/AArch64/AArch64FrameLowering.cpp:744: warning: enumeral and non-enumeral type in conditional expression [-Wextra]
   743 |     Register TargetReg = RealignmentPadding
       |     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   744 |                              ? findScratchNonCalleeSaveRegister(&MBB)
       |                              ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   745 |                              : AArch64::SP;
       |
 ../lib/Target/AArch64/AArch64FrameLowering.cpp:803: warning: enumeral and non-enumeral type in conditional expression [-Wextra]
   802 |     Register ScratchReg = RealignmentPadding
       |     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   803 |                               ? findScratchNonCalleeSaveRegister(&MBB)
       |                               ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   804 |                               : AArch64::SP;
       |

Previously, RISCVInsertReadWriteCSR inserted an FRM swap for any value
other than 7 and restored the original value right after the vector
instruction. This is inefficient if multiple vector instructions use the
same rounding mode if the next vector instruction uses a different
explicit rounding mode.

This patch implements a local optimization to solve the above problem.
We assume the starting rounding mode of the basic block is "dynamic."
When iterating through a basic block and encountering an instruction
whose rounding mode is not the same as the current rounding mode, we
change the current rounding mode and save the current rounding mode if
needed. And we may need to restore FRM when encountering function call,
inline asm and some uses of FRM.

The advanced version of this is to perform cross basic block analysis
for the starting rounding mode of each basic block.

This class is not specific to "Tr"(Transpose). It is
just for a normal load.

This patch is split off from #77342

- Correct for CodeSize cost that 1 instruction is not included. 3 is
from {VMV.S, ReductionOp, VMV.X}
- Add SplitCost
Unordered reduction chain a series of VADD/VFADD/... which scales with
LMUL.
 Ordered reductions chain a series of VFREDOSUMs.
- Use MVT to estimate VL.

Progress on https://github.com/openxla/iree/issues/16181

Promoted BMI instructions were supported in #73899

llvm-project/llvm/lib/Transforms/Instrumentation/MemProfiler.cpp:375:21:
 error: unused variable 'DL' [-Werror,-Wunused-variable]
  const DataLayout &DL = I->getModule()->getDataLayout();
                    ^
1 error generated.

As discussed in https://github.com/llvm/llvm-project/pull/79244, the
sized memory access callback is leftover stuff carried over from Asan,
can removed from the instrumentation.

Unlike ASan, MemProf uses the same memory access callback(inline
sequence) for different size memory access, remove unneeded TypeSize
stored in InterestingMemoryAccess.

…a once  (#76119)"

This reverts commit f0c38703 because it
causes an lldb test to fail on a missing import on Mac.

https://logs.chromium.org/logs/fuchsia/buildbucket/cr-buildbucket/8758053465398947297/+/u/lldb/test/stdout

These functions always return -1 and set 'errno'.

If we're lowering an e8 m8 shuffle and we have an index value greater than
255, we have no available space to generate an e16 index vector.  The
code had originally handled this correctly, but in a recent refactoring
I had moved the single source code above the check, and thus broke the
single source by accident.

I have a change on review to rework this (https://github.com/llvm/llvm-project/pull/79330), but for now, go with the most obvious fix.

Triggered by discussion on https://github.com/llvm/llvm-project/pull/79330.  In the process of writing this, realized one of my recent refactorings appears to have broken the legalization for the single source case here.  Fix to follow in separate patch.

The standard requires `limits.h` constants to be used in preprocessors.
So we use `__SIZEOF_LONG__` instead of `sizeof(long)` to define
`LONG_WIDTH`. The macro `__SIZEOF_LONG__` seems to be available on both
clang and gcc since at least version 9.

Changed so that we also update DW_AT_stmt_list for DWARF5 TUs. BOLT was
doing it for DWARF4, but it wasn't doing it for DWARF5.

msan-handle-asm-conservative is enabled by KMSAN by default.
Enable the userspace by default as well after #77393.

I originally thought to try to guesstimate the hardware watchpoint index
number that a Resource was associated with, but gdb remote serial
protocol doesn't give us the hardware register index used so it was only
a guess. I changed my mind and simply use ever-incrementing ID numbers
for the WatchpointResources, but forgot to remove the SetID method.

In `[lldb] [mostly NFC] Large WP foundation: WatchpointResources
(#68845)` I added a new template StopPointSiteList to combine
WatchpointResourceList and BreakpointSiteList. But I didn't remove the
now-unused WatchpointResourceList class. This patch fixes that.

a freebsd dev member reported a symbol conflict and intercepting this
had little value anyway.

This relands commit f890f010.

The result value of `getelementptr inbounds (TY, null, not zero)` is a poison value.
We can think of it as undefined behavior.

This relands commit b6a0be8c.

Return undefined to a noundef return value is undefined.

Example:

```
define noundef i32 @test_ret_noundef(i1 %cond) {
entry:
  br i1 %cond, label %bb1, label %bb2
bb1:
  br label %bb2
bb2:
  %r = phi i32 [ undef, %entry ], [ 1, %bb1 ]
  ret i32 %r
}
```

Turns out the problem with
https://github.com/llvm/llvm-project/issues/60013 is due to the fact
that order of operation is unspecified in C++:
https://en.cppreference.com/w/cpp/language/eval_order. A small example
of where this manifests with MSVC can be seen here
https://ooo.godbolt.org/z/bxqKeqzqn.

This patch does the following:
* Removes the addition operations where we sequence more than one
side-effect based expression.
* Removes test guards to now run on Windows

This is to fix the bug reported in
https://discourse.llvm.org/t/whats-the-recommended-way-to-use-prop-dict/75921



When `prop-dict` is used in the assembly format, `attr-dict` should
print discardable attributes only.

Co-authored-by: Arthurq Qiu <arthurq@nvidia.com>

weak ordering.
Try to make PHICompare to meat strict weak ordering criteria.

async just takes an integral value, but it has a little bit of special
rules in sema, so it is implemented slightly differently than int-expr.

This patch implements async parsing.