Reserve X18 even when -fsanitize=shadow-call-stack is not enabled.

Based on: https://reviews.llvm.org/D143355

Reviewed by: asb, samitolvanen, phosek, MaskRay

Differential Revision: https://reviews.llvm.org/D145999

Currently clang emits error when both always_inline and target
attributes are on callee, but caller doesn't have some feature.

This patch makes clang emit error when caller cannot meet target feature
requirements from an always-inlined callee.

Reviewed By: erichkeane

Differential Revision: https://reviews.llvm.org/D143479

Allows applying nofpclass to matrix arguments.

Set this on any source level floating-point type argument,
return value, call return or outgoing parameter which is lowered
to a valid IR type for the attribute. Currently this isn't
applied to emitted intrinsics since those don't go through
ABI code.

Cover more cases in preparation for making greater use
of fcmp based lowerings. Also add more tests for the inverted
cases. Test iszero | isnan test masks. We should probably just
generate every combination of test masks.

/data/llvm-project/mlir/lib/Dialect/Tensor/Utils/Utils.cpp:62:11: error: comparison of integers of different signs: 'int64_t' (aka 'long') and 'size_t' (aka 'unsigned long') [-Werror,-Wsign-compare]
  if (dim >= shape.size())
      ~~~ ^  ~~~~~~~~~~~~
1 error generated.

/data/llvm-project/mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp:484:8: error: unused variable 'appendIndex' [-Werror,-Wunused-variable]
  auto appendIndex = [&](Value val, SmallVector<Value> &dynIndices,
       ^
1 error generated.

Reviewed By: springerm

Differential Revision: https://reviews.llvm.org/D145135

Reviewed By: sivachandra

Differential Revision: https://reviews.llvm.org/D146049

This builtin will be converted to llvm.set.rounding intrinsic
in IR level and should be work with "#pragma STDC FENV_ACCESS ON"
since it changes default FP environment. Users can change rounding
mode via this builtin without introducing libc dependency.

Reviewed by: andrew.w.kaylor, rjmccall, sepavloff, aaron.ballman
Differential Revision: https://reviews.llvm.org/D145765


Signed-off-by: jinge90 <ge.jin@intel.com>

Fix recently introduced error and further generalize
pattern matching for accepted HOST string

With opaque pointers, all function pointer types are the same, meaning there should be no bitcasts.

Internal benchmarks with SampleFDO look neutral.

This was added in D36333.

Reviewed By: tejohnson, davidxl

Differential Revision: https://reviews.llvm.org/D146099

The recent bundler patch (e48ae0db) introduced a few errors
in two clang/Driver tests, and in the bundler documentation

The test is failing on the PS4/PS5 bots:
https://lab.llvm.org/buildbot/#/builders/139/builds/37475
https://lab.llvm.org/buildbot/#/builders/216/builds/18354

When the affine.parallel op was introduced, affine utilities weren't
extended to handle it. Extending these is straightforward and natural
given that addAffineParallelOpDomain has also been added.
Update/complete memref region compute to account for affine.parallel
ops. Handle failure cleanly.

Add and expose utilities missing for affine.parallel to be consistent
with affine.for.

All of these allow various affine passes to work with a combination of
affine.parallel and affine.for ops.

Differential Revision: https://reviews.llvm.org/D145669

The two methods don't belong in BinaryFunction methods.
Move the dispatch tables into target-specific MCPlusBuilder methods.

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D131813

Reviewed By: craig.topper, asb

Differential Revision: https://reviews.llvm.org/D146008

Pre-calculate the register size table in MCPlusBuilder constructor,
similar to `AliasMap`/`SmallerAliasMap` in `initAliases`.

Reviewed By: #bolt, rafauler

Differential Revision: https://reviews.llvm.org/D145828

This allows building the compiler builtins library for the Armv8-M
Baseline architecture. It can be built in the same way as other
baremetal targets using the appropriate '--target' flag
(e.g. --target=armv8m.base-eabi).

NOTE: As with the other Cortex-M targets, only the builtins library is
supported. There is no support for sanitizers, etc.

The armv8m.base architecture is a superset of armv6m, so adding it to
the cmake files using thumb1_SOURCES is almost enough for it to compile.
Minor changes are needed to divsi3 and udivsi3, because armv8m.base does
have support for div instructions but not mov with an immediate operand.

Reviewed By: MaskRay, peter.smith

Differential Revision: https://reviews.llvm.org/D143297

Simplifies D145687

Reviewed By: #bolt, rafauler

Differential Revision: https://reviews.llvm.org/D145972

Adds perf event listeners when RTDyldObjectLinkingLayer is used in -jit-kind=orc
mode.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D126214

Differential Revision: https://reviews.llvm.org/D144125

Reviewed By: kuhar

Differential Revision: https://reviews.llvm.org/D145079

This fixes test failures on AArch64 with libgcc-13:

Clang :: Interpreter/global-dtor.cpp
Clang-Unit :: Interpreter/./ClangReplInterpreterTests/2/4

Reviewed By: lhames, v.g.vassilev

Differential Revision: https://reviews.llvm.org/D146067

The patch handles fixed type strict-fp by new RISCVISD::STRICT_ prefixed
isd nodes.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D145900

[Clang] Fix ClassifyImplicitMemberAccess to handle cases where the access in an unevaluated context is not within a CXXRecordDecl or CXXMethodDecl

ClassifyImplicitMemberAccess assumes that if we are not in a static context then
the DeclContext must be a CXXRecordDecl or a CXXMethodDecl. In the case of the
unevaluated context this may not be true.

This will lead to a crash because contextClass will remain a nullptr.

Fixes: https://github.com/llvm/llvm-project/issues/37792
Fixes: https://github.com/llvm/llvm-project/issues/48405

Differential Revision: https://reviews.llvm.org/D142490

For now, I have introduced `llvm::tmp::getValueType(Rec)` as a copy from
`CodeGenTarget.cpp`. This will be removed in the near future, when
IntrinsicEmitter will not depend on MVT.

Differential Revision: https://reviews.llvm.org/D143844

Differential Revision: https://reviews.llvm.org/D143844