For fixed and scalable vectors, each intrinsic x is lowered to vmx.mm,
dropping the mask, which is safe to do as masked-off elements are
undef anyway.

Differential Revision: https://reviews.llvm.org/D115339

Linalg named ops lowering are moved to a separate pass. This allows TOSA
canonicalizers to run between named-ops lowerings and the general TOSA
lowerings. This allows the TOSA canonicalizers to run between lowerings.

Reviewed By: NatashaKnk

Differential Revision: https://reviews.llvm.org/D116057

A prevectorized loop may contain multiple statements, in which case
isl_schedule_node_band_sink will sink the vector band to multiple
leaves. Instead of statically assuming a specific tree structure after
sinking, add a SIMD marker to all inner bands.

Fixes llvm.org/PR52637

Largely split out of D116199 to keep that PR smaller.

As suggested in D115312.

It was missing the cast to `bool` in `bool(__t.empty())`.
It was wrongly using `std::forward` in some places.

Differential Revision: https://reviews.llvm.org/D115312

Differential Revision: https://reviews.llvm.org/D116198

The Linux kernel has a make macro called cc-option that invokes the
compiler with an option in isolation to see if it is supported before
adding it to CFLAGS. The exit code of the compiler is used to determine
if the flag is supported and should be added to the compiler invocation.

A call to cc-option with '-mno-outline-atomics' was added to prevent
linking errors with newer GCC versions but this call succeeds with a
non-AArch64 target because there is no warning from clang with
'-mno-outline-atomics', just '-moutline-atomics'. Because the call
succeeds and adds '-mno-outline-atomics' to the compiler invocation,
there is a warning from LLVM because the 'outline-atomics target
feature is only supported by the AArch64 backend.

$ echo | clang -target x86_64 -moutline-atomics -Werror -x c -c -o /dev/null -
clang-14: error: The 'x86_64' architecture does not support -moutline-atomics; flag ignored [-Werror,-Woption-ignored]

$ echo $?
1

$ echo | clang -target x86_64 -mno-outline-atomics -Werror -x c -c -o /dev/null -
'-outline-atomics' is not a recognized feature for this target (ignoring feature)

$ echo $?
0

This does not match GCC's behavior, which errors when the flag is added
to a non-AArch64 target.

$ echo | gcc -moutline-atomics -x c -c -o /dev/null -
gcc: error: unrecognized command-line option ‘-moutline-atomics’; did you mean ‘-finline-atomics’?

$ echo | gcc -mno-outline-atomics -x c -c -o /dev/null -
gcc: error: unrecognized command-line option ‘-mno-outline-atomics’; did you mean ‘-fno-inline-atomics’?

$ echo | aarch64-linux-gnu-gcc -moutline-atomics -x c -c -o /dev/null -

$ echo | aarch64-linux-gnu-gcc -mno-outline-atomics -x c -c -o /dev/null -

To get closer to  GCC's behavior, issue a warning when
'-mno-outline-atomics' is used without an AArch64 triple and do not add
'{-,+}outline-atomic" to the list of target features in these cases.

Link: https://github.com/ClangBuiltLinux/linux/issues/1552

Reviewed By: melver, nickdesaulniers

Differential Revision: https://reviews.llvm.org/D116128

I added `PPC32Got2Section` D62464 to support .got2 but did not implement .got2
in another output section.

PR52799 has a linker script placing .got2 in .rodata, which causes a null
pointer dereference because a MergeSyntheticSection's file is nullptr.
Add the support.

This option is per process anyway. I'd like to add more options, but
having them as parameters of __sanitizer_symbolize_code looks
inconvenient.

Reviewed By: browneee

Differential Revision: https://reviews.llvm.org/D116201

-no-canonical-prefixes is not needed if we omit "clang" from CHECK lines.
"-cc1" is sufficient to anchor the line we want to test.
--target= is preferred over Separate form -target.

D116202 uses all availible slots.

A variable was named in a way that doesn't match the format. This patch
renames it to match the format.

Differential Revision: https://reviews.llvm.org/D116228

Reviewed By: vettoreldaniele, GMNGeoffrey

Differential Revision: https://reviews.llvm.org/D116222

There is a slight speed-up.

This reverts commit ab3640aa.

Reviewed By: kstoimenov

Differential Revision: https://reviews.llvm.org/D116223

Removing dead frame indices for VGPR to AGPR spills is incorrect
when the frame index is shared by multiple objects, which may
occur due to stack slot coloring. The problem is that subsequent
code that processes the other object will assert because the stack
frame index is marked dead.

Removing dead frame indices is needed prior to stack slot
coloring, which is what happens with SGPR to VGPR spills. These
spills are lowered prior to stack slot coloring, but the VGPR
to AGPR spills are processed afterwards during the Prolog/Epilog
Inserter pass. This patch marks the VGPR to AGPR spill slot as
dead if the slot is not used by another object.

Differential Revision: https://reviews.llvm.org/D115996

This will allow linking in the callbacks directly instead of using PLT.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D116182

Reviewed By: #libc, Quuxplusone, Mordante

Differential Revision: https://reviews.llvm.org/D116175

-0.0 requires a constant pool. +0.0 can be made with vmv.v.x x0.

Not doing this in getNeutralElement for fear of changing other targets.

Differential Revision: https://reviews.llvm.org/D115978

During the review of D115991 @vitaut pointed out the enum shouldn't
depend on whether or not _LIBCPP_HAS_NO_INT128 is defined. The current
implementation lets the enum's ABI depend on this configuration option
without a good cause.

Reviewed By: ldionne, #libc

Differential Revision: https://reviews.llvm.org/D116120

This adds support for strict conversions between fp types and between
integer and fp.

NOTE: RISCV has static rounding mode instructions, but the constrainted
intrinsic metadata is not used to select static rounding modes. Dynamic
rounding mode is always used.

Differential Revision: https://reviews.llvm.org/D115997

Converts concat_vectors(Vd, trunc(smin(smax Vm, -2^n), 2^n-1) to
sqxtn2(Vd, Vm). Deliberately not handling v2i64 ~> v2i32 as the
min/max nodes are not legal (same thing we did for the SQXTN
patterns in https://reviews.llvm.org/D103263).

Differential Revision: https://reviews.llvm.org/D116105

Delete inst-select-insert.xfail.mir.
G_INSERT instructions in inst-select-insert.xfail.mir are no longer
legal after D114198. This breaks build bots, since builds with
LLVM_ENABLE_ASSERTIONS=Off don't check for legality and report cannot
select while build with LLVM_ENABLE_ASSERTIONS=On reports instruction
is not legal.

This patch adds a toolchain (TC) for SPIR-V along with the
following changes in Driver and base ToolChain and Tool.
This is required to provide a mechanism in clang to bypass
SPIR-V backend in LLVM for SPIR-V until it lands in LLVM and
matures.

The SPIR-V code is generated by the SPIRV-LLVM translator tool
named 'llvm-spirv' that is sought in 'PATH'.

The compilation phases/actions should be bound for SPIR-V in
the meantime as following:

    compile -> tools::Clang
    backend -> tools::SPIRV::Translator
    assemble -> tools::SPIRV::Translator

However, Driver’s ToolSelector collapses compile-backend-assemble
and compile-backend sequences to tools::Clang. To prevent this,
added new {use,has}IntegratedBackend properties in ToolChain and
Tool to which the ToolSelector reacts on, and which SPIR-V TC
overrides.

Linking of multiple input files is currently not supported but
can be added separately.

Differential Revision: https://reviews.llvm.org/D112410



Co-authored-by: Henry Linjamäki <henry.linjamaki@parmance.com>

Fix issue in TargetLowering::expandROT where we only attempt to flip a rotation if the other direction has better support - this matches TargetLowering::expandFunnelShift

This allows us to enable ISD::ROTR lowering on SSE targets, which particularly simplifies/improves codegen for splat amount and AVX2 per-element shifts.

Adding following fold opportunity:
((A | B) ^ A) & ((A | B) ^ B) --> 0

Reviewed By: spatel, rampitec

Differential Revision: https://reviews.llvm.org/D115755

The loop vectorizer can interleave scalar loops even if it doesn't
vectorize them. I don't believe we intended to enable this when
we enabled interleaving for vector instructions.

Disable interleaving for VF=1 like X86 and AMDGPU already do. Test
lifted from AMDGPU.

Differential Revision: https://reviews.llvm.org/D115975

[X86] isVectorShiftByScalarCheap - vXi8 select(shift(x,splat0),shift(x,splat1)) is better than shift(x,select(splat0,splat1))

Even though we don't have vXi8 vector shifts (apart from XOP), it is still better to prefer shift (or funnel-shift/rotate) by scalar where possible.

https://llvm.godbolt.org/z/6ss6ffTxv

Differential Revision: https://reviews.llvm.org/D116191

This was casting the address to its own element type, which is
a no-op.

This does exactly what this code manually implemented.

Add an overload for an Address and a single non-constant offset.
This makes it easier to preserve the element type and adjust the
alignment appropriately.

Artifact combiner is not able to access individual elements after using
LCMTy style merge/unmerge, extract and insert to change vector number of
elements (pad with undef or split to sub-vector instructions).
Use unmerge to individual elements instead and then merge elements into
requested types.
Change argument lowering for vectors and moreElementsVector to use
buildPadVectorWithUndefElements and buildDeleteTrailingVectorElements.
FewerElementsVector had a few helpers that had different behavior,
introduce new helper for most of the opcodes.
FewerElementsVector helper is more flexible since it can create leftover
instruction smaller then requested type (useful in case target wants to
avoid pad with undef and use fewer registers). If target does not want
leftover of different type it should call more elements first.
Some helpers were performing more elements first to have split without
leftover. Opcodes that used this helper use clampMaxNumElementsStrict
(does more elements first) in LegalizerInfo to avoid test changes.
Fixes failures caused by failing to combine artifacts created during
more/fewer elements vector.

Differential Revision: https://reviews.llvm.org/D114198

Precommit for D114198 (Rework more/fewer elements for vectors).
Regenerate auto-generated mir tests for vectors (use CHECK-NEXT instead
of CHECK). Remove -global-isel-abort=0 where it is no longer needed.
Add mir tests for different AMDGPU sub-targets and they way they lower
function vector arguments (tests for legalization artifact combiner).

Reference VE manual and documentations in CompilerWriterInfo.

Reviewed By: kaz7

Differential Revision: https://reviews.llvm.org/D116212