- Nov 02, 2020
-
-
Craig Topper authored
The fshr intrinsic with same inputs produces rotr ISD node. The fshl intrinsic produces rotl ISD node. There were only test cases and isel patterns for the fshl/rotl case. This patch adds fshr/rotr test cases.
-
Craig Topper authored
This reverts 78191725 and recommits 78191725. I've changed getRegForInlineAsmConstraint to not use a std::pair of Register in a previous commit. Hopefully that fixes the reported issue with expensive checks on Windows. I'm still not sure exactly why this commit removing an include affected a different file. Original message: RISCVRegisterInfo.h is part of the CodeGen layer. The Utils library is intended to be shared with the MC layer so shouldn't use files from the CodeGen layer. The register enum names are already available from RISCVMCTargetDesc.h. It appears what was coming from this include was a transitive include of the Register class which I've replaced with MCRegister. Register has a constructor from MCRegister so it should be convertible.
-
Craig Topper authored
The return value of this interface still uses an 'unsigned' on all targets. So we convert Register back to unsigned at the end. I'm hoping this will prevent the issue that caused the revert of D90322.
-
Nikita Popov authored
Instead of performing a sequence of pairwise additions, directly construct a multi-operand add expression. This should be NFC modulo any SCEV canonicalization deficiencies.
-
Florian Hahn authored
When deleting a VPValue, all users must already by deleted. Add an assertion to make sure and catch violations.
-
David Green authored
-
- Nov 01, 2020
-
-
Qiu Chaofan authored
Unsigned 32-bit or shorter integer to ppcf128 conversion are currently expanded as signed-to-double with an extra fadd to 'complement'. But on PowerPC we have native instruction to directly convert unsigned to double since ISA v2.06. This patch exploits it. Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D89786
-
Nathan James authored
-
Ilya Bukonkin authored
-
Christudasan Devadasan authored
-
Christudasan Devadasan authored
It should be enabled only when the load alignment is at least 8-byte. Fixes: SWDEV-256824 Reviewed By: foad Differential Revision: https://reviews.llvm.org/D90404
-
Fangrui Song authored
-
Fangrui Song authored
-
Fangrui Song authored
-
Sam Clegg authored
This test was checking behaviour that only exists in the debug configuration so will fail in release builds. Perhaps there is way to keep this test around and only run it in debug builds but for now I'm removing so fix the release builders. Differential Revision: https://reviews.llvm.org/D90542
-
Ayke van Laethem authored
These expansions were rather inefficient and were done with more code than necessary. This change optimizes them to use expansions more similar to GCC. The code size is the same (when optimizing for code size) but somehow LLVM reorders blocks in a non-optimal way. Still, this should be an improvement with a reduction in code size of around 0.12% (when building compiler-rt). Differential Revision: https://reviews.llvm.org/D86418
-
River Riddle authored
Switch to an index based loop instead of using enumerate.
-
Florian Hahn authored
This patch updates DSE + MemorySSA to use the same check as the legacy implementation to determine if a location is killed by a free call. This changes the existing behavior so that a free does not kill locations before the start of the freed pointer. This should fix PR48036.
-
Florian Hahn authored
The new test cases are inspired by PR48036.
-
Reid Kleckner authored
I don't see any warnings from lld.wasm locally. Needs more investigation.
-
Reid Kleckner authored
I had envisioned the ghash step as a big up front step, but as currently written, the timers are nested, and we are notionally adding types from objects, so we might as well arrange the timers this way.
-
Simon Pilgrim authored
-
Kostya Kortchinsky authored
This CL introduces the Fuchsia versions of the existing platform specific functions. For Fuchsia, we need to track the VMAR (https://fuchsia.dev/fuchsia-src/reference/kernel_objects/vm_address_region) of the Guarded Pool mapping, and for this purpose I added some platform specific data structure that remains empty on POSIX platforms. `getThreadID` is not super useful for Fuchsia so it's just left as a stub for now. While testing the changes in my Fuchsia tree, I realized that `guarded_pool_allocator_tls.h` should have closed the namespace before including `GWP_ASAN_PLATFORM_TLS_HEADER`, otherwise drama ensues. This was tested in g3, upstream LLVM, and Fuchsia (with local changes). Differential Revision: https://reviews.llvm.org/D90483
-
Florian Hahn authored
This reverts the revert commit a1b53db3. This patch includes a fix for a reported issue, caused by matchSelectPattern returning UMIN for selects of pointers in some cases by looking to some connected casts. For now, ensure integer instrinsics are only returned for selects of ints or int vectors.
-
Mark de Wever authored
Adds a diagnostic when the user annotates an `if constexpr` with a likelihood attribute. The `if constexpr` statement is evaluated at compile time so the attribute has no effect. Annotating the accompanied `else` with a likelihood attribute has the same effect as annotating a generic statement. Since the attribute there is most likely not intended, a diagnostic will be issued. Since the attributes can't conflict, the "conflict" won't be diagnosed for an `if constexpr`. Differential Revision: https://reviews.llvm.org/D90336
-
Mark de Wever authored
The attribute has no effect on a do statement since the path of execution will always include its substatement. It adds a diagnostic when the attribute is used on an infinite while loop since the codegen omits the branch here. Since the likelihood attributes have no effect on a do statement no diagnostic will be issued for do [[unlikely]] {...} while(0); Differential Revision: https://reviews.llvm.org/D89899
-
- Oct 31, 2020
-
-
Paul C. Anagnostopoulos authored
They occurred in one NVPTX file and some test files. Differential Revision: https://reviews.llvm.org/D90513
-
David Sanders authored
On Windows the --use-color option cannot be used for its originally intended purpose of forcing color when piping stdout, since Windows does not use ANSI escape codes by default. This change turns on ANSI escape codes on Windows when forcing color to a non-displayed stdout (e.g. piped).
-
David Green authored
If the elt size is unknown due to it being a pointer, a comparison against 0 will cause an assert. Make sure the elt size is large enough before comparing and for the moment just return the scalar cost.
-
Serge Pavlov authored
This test fails on buildbots where CPU architecture does not fully support constrained intrinsics.
-
Simon Pilgrim authored
This is the last of the rotate->funnel shift InstCombine generalizations for PR46896 We still have foldGuardedRotateToFunnelShift to deal with in AggressiveInstCombine Differential Revision: https://reviews.llvm.org/D90382
-
Simon Pilgrim authored
Fixes a number of cppcheck remarks.
-
Simon Pilgrim authored
Fixes a cppcheck remark.
-
Simon Pilgrim authored
Fixes a number of cppcheck remarks.
-
Simon Pilgrim authored
Fixes a number of cppcheck remarks.
-
Andrea Di Biagio authored
This is likely to be a regressigion introduced by my last refactoring of the LSUnit (commit 5578ec32). Before this patch, the "CurrentStoreBarrierGroupID" index was not correctly reset on store barrier executions. This was leading to unexpected crashes like the one reported as PR48024.
-
Simon Pilgrim authored
Silences cppcheck mismatch warnings.
-
Simon Pilgrim authored
-
Simon Pilgrim authored
Fixes cppcheck warning.
-
Simon Pilgrim authored
X86OutgoingValueHandler already has a MIB member
-