Fix https://github.com/llvm/llvm-project/issues/60392

```
// a.cc
void raise() { throw 42; }
bool foo() {
  try { raise(); } catch (int) { return true; }
  return false;
}
int main() { foo(); }
```

```
clang++ --target=x86_64-linux-gnu -fno-pic -mcmodel=large -no-pie -fuse-ld=lld -z notext a.cc -o a && ./a
clang++ --target=aarch64-linux-gnu -fno-pic -no-pie -fuse-ld=lld -Wl,--dynamic-linker=/usr/aarch64-linux-gnu/lib/ld-linux-aarch64.so.1 -Wl,-rpath=/usr/aarch64-linux-gnu/lib -z notext a.cc -o a && ./a
```
Both commands fail because we produce a dynamic relocation for
R_X86_64_64/R_AARCH64_ABS64 in .eh_frame which will be adjusted to a wrong
offset by `SectionBase::getOffset` after D122459.

Since GNU ld uses a canonical PLT entry instead of a dynamic relocation for
.eh_frame, we follow suit as well to avoid the issue.

Mips has an ABI issue (https://github.com/llvm/llvm-project/issues/5837) and we
don't implement GNU ld's DW_EH_PE_absptr conversion. mips64-eh-abs-reloc.s wants
a dynamic relocation, so keep the original behavior for EM_MIPS.

Differential Revision: https://reviews.llvm.org/D143136

Revert "[SelectionDAG] Add missing setValue calls in visitIntrinsicCall"

This reverts commit 0c64e1b6.
This reverts commit 1142e6c7.

It spuriously added !pcsections where they shouldn't be. See added test
case in test/CodeGen/X86/pcsections.ll as an example. The reason is that
the SelectionDAG chains operations in a basic block as "operands"
pointing to preceding instructions. This resulted in setting the
metadata on _all_ instructions preceding the one that should have the
metadata.

Reverting for now because the semantics of !pcsections was completely
buggy now.

Remove alignment matching in tests to avoid ABI compatibility issues

Removes the forwarding header `llvm/Support/AArch64TargetParser.h`.

I am proposing to do this for all the forwarding headers left after
rGf09cf34d - for each header:
- Update all relevant in-tree includes
- Remove the forwarding Header

Differential Revision: https://reviews.llvm.org/D140999

Do not check for version symbol support if the necessary linker flag is
not supported.

Differential Revision: https://reviews.llvm.org/D143200

This reverts commit d708a186 (and typo fix e4bc9898). It causes a compilation error for this:

```
struct StringLiteral {
  template <int N>
  StringLiteral(const char (&array)[N])
      __attribute__((enable_if(N > 0 && N == __builtin_strlen(array) + 1,
                               "invalid string literal")));
};

struct Message {
  Message(StringLiteral);
};

void Func1() {
  auto x = Message("x");  // Note: this is fine

  // Note: "xx\0" to force a different type, StringLiteral<3>, otherwise this
  // successfully builds.
  auto y = [&](decltype(Message("xx"))) {};

  // ^ fails with: repro.cc:18:13: error: reference to local variable 'array'
  // declared in enclosing function 'StringLiteral::StringLiteral<3>'

  (void)x;
  (void)y;
}
```

More details posted to D124351.

GFX11 renames:
v_cvt_pknorm_i16_f32 to v_cvt_pk_norm_i16_f32
v_cvt_pknorm_u16_f32 to v_cvt_pk_norm_u16_f32

Accept the old name as an alias.

Fixes https://github.com/llvm/llvm-project/issues/60334

Differential Revision: https://reviews.llvm.org/D143266

Differential Revision: https://reviews.llvm.org/D143262

Differential Revision: https://reviews.llvm.org/D142992

This is split out of D140908 as suggested.

Differential Revision: https://reviews.llvm.org/D143184

Differential Revision: https://reviews.llvm.org/D140874

Differential Revision: https://reviews.llvm.org/D143271

The bots report:
LLVM ERROR: MachO doesn't support COMDATs, 'f' cannot be lowered.

[AMDGPU] Modify adjustInliningThreshold to also consider the cost of passing function arguments through the stack

A regression from when new PM got enabled as default. Functions with a big number of instructions will elide getting inlined but do not consider the cost of passing arguments over stack if there are a lot of function arguments. This patch attempts to add a heuristic for AMDGPU's function calling convention that also considers function arguments passed through the stack.

Reviewed By: #amdgpu, arsenm

Differential Revision: https://reviews.llvm.org/D140242

The revision uses tablegen to convert multiple atomic and comparison
related enums automatically rather than using hand coded functions
in the import and export from and to LLVM IR.

The revision also adds additional binary operation cases to the
AtomicBinOp enum that have not been supported till now. It also
introduces the possibility to define unsupported enum cases that exist
only in LLVM IR and that are not imported into MLIR. These unsupported
cases are helpful to handle sentinel values such as BAD_BINOP that
LLVM commonly uses to terminate its enums.

Reviewed By: Dinistro

Differential Revision: https://reviews.llvm.org/D143189

This reverts commit 60dcc70e.

This breaks builders, e.g.
https://lab.llvm.org/buildbot/#/builders/36/builds/30036

Symbol/Header::all() calls

Just pop the pointer.

This NFC (intended) patch has several small changes:
* It renames PredicationStyle to TailFoldingStyle.
* It renames TTI.emitActiveLaneMask() to TTI.getPreferredTailFoldingStyle()
* Simplifies some of its uses in the LoopVectorizer

Rationale: To my surprise PredicationStyle::None did not mean 'no
predication', but rather 'no active lane mask intrinsic', such that the
predicate is created using a splat + compare with stepvector. The enum is
also highly specific to tail folding, so it seems better to name this
around that feature, i.e. 'tail folding style'.

This also makes it more amenable to extend it to other tail folding styles,
such as the one added in D142109.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D142887

ValueTracking attempts to match compare+select patterns to FP min/max
operations, but it was created before the newer IEEE-754-2019
minimum/maximum ops were defined. Ie, matchSelectPattern() does not
account for the -0.0/+0.0 behavior that is specified in the newer
standard.

FMINIMUM/FMAXIMUM nodes were created to map to the newer standard:

/// FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0
/// as less than 0.0. While FMINNUM_IEEE/FMAXNUM_IEEE follow IEEE 754-2008
/// semantics, FMINIMUM/FMAXIMUM follow IEEE 754-2018 draft semantics.

We could adjust ValueTracking to deal with signed zero, but it seems like
a moot point given the divergent NaN behavior discussed in D143056, so just
delete this possibility to avoid bugs when converting IR to SDAG.

Differential Revision: https://reviews.llvm.org/D143106

This test is supposed to work in arm64.

Differential Revision: https://reviews.llvm.org/D143265

These were using ” ("right double quotation mark") instead of
the usual ". This means CMake took the value literally and you
got:
```
CMake Error at CMakeLists.txt:139 (MESSAGE):
  ”libc” isn't a known project:
  bolt;clang;clang-tools-extra;compiler-rt;cross-project-tests;libc;libclc;lld;lldb;mlir;openmp;polly;pstl;flang.
  Did you mean to enable it as a runtime in LLVM_ENABLE_RUNTIMES?
```
`="libc"` works fine.

Reviewed By: lntue

Differential Revision: https://reviews.llvm.org/D143254

With the current set of opcodes, this saves 3460 lines in the generated
Opcodes.inc in release builds (-17%).

Differential Revision: https://reviews.llvm.org/D142694

For atomics metadata, we can make data race analysis more efficient by
entirely ignoring functions that include memory accesses but which only
access non-escaping (non-shared) and/or non-mutable memory. Such
functions will not be considered to be covered by "atomics" metadata,
resulting in the following benefits:

  1. reduces "covered" metadata; and
  2. allows data race analysis to skip such functions.

Reviewed By: dvyukov

Differential Revision: https://reviews.llvm.org/D143159

Adapted from the existing shuffle-of-fneg tests.

The original implementation of the transform interpreter pass base was
cloning the entire transform IR in presence of PDL-related operations to
avoid concurrency issues when running the pass with the same transform
IR on multiple operations of the payload IR. The root cause of those
issues is the `transform.pdl_match` operation that was moving the PDL
pattern definition operation into a new module, consumed by the PDL
interpreter and leading to a race. Clone the pattern operation instead.
This avoids the race as well as the cost for transform IR that doesn't
use PDL.

Depends on D142729.

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D142962

The transform dialect infrastructure does not provide a default
interpreter pass and instead expects users to create their own to ensure
all relevant extensions and dependent dialects are loaded. Provide a
base class for implementing such passes that includes the additional
facilities for debugging and is aware of the multithreaded nature of
pass execution.

Reviewed By: pifon2a, nicolasvasilache

Differential Revision: https://reviews.llvm.org/D142729

Implement MaterializeTemporaryExpr for primitive types.

Differential Revision: https://reviews.llvm.org/D136017

The code did not propagate the result optionality for subroutine.
Make the result of genIntrinsicRef optional.

Differential Revision: https://reviews.llvm.org/D143251

The current behavior for AMX macros is:

```
gcc -march=native -dM -E - < /dev/null | grep TILE

clang -march=native -dM -E - < /dev/null | grep TILE
```

which is not ideal.  Change `__AMXTILE__` and friends to `__AMX_TILE__` (i.e.
have an underscore in them).  This makes GCC and Clang agree on the naming of
these AMX macros to simplify downstream user code.

Fix this for `__AMXTILE__`, `__AMX_INT8__`, `__AMX_BF16__`, and `__AMX_FP16__`.

Differential Revision: https://reviews.llvm.org/D143094

While we potentially need to align partially mapped structs more than
the first member, we do not need to align past the struct itself. This
prevents us from moving the base pointer past the struct beginning too.

See https://reviews.llvm.org/D142508 for a discussion.

Reviewed By: pavelkopyl, grokos, jhuber6

Differential Revision: https://reviews.llvm.org/D142586

This reverts commit d65c3bf3.

Differential Revision: https://reviews.llvm.org/D141858

Inspired by Issue #60464 - wel can add/enable additional intrinsics when we add expansion support

`llvm.load` op has nonTemporal field which is missing for `memref.load` and `memref.store`. This revision first adds nonTemporal field to memref's load/store op, then it lowers the field to llvm.load/store ops.

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D142616