For migration from Seq[String] port style, not yet fully implemented

Performing a pad on SInt literals results in linting warnings in Verilator.
This commit replaces pad operations on literal values with a literal of the
correct width.

These debug transforms modify the default transforms to include additional
checking passes to detect things like invalid types inserted by passes.
This commit augments the current suite of tests to detect #169 and the like.

Fixes #172

Bit selecting a literal resulted in invalid Verilog. Legalize now deals with
this by replacing any bits select of UInt or SInt literals with a new literal
composed of the selected bits. Legalize also is now run after PadWidths because
that pass introduces this issue.

Fixes #170

Legalize will wrap the rhs of a connect statement with a bit select primop if
the lhs is of smaller width than the rhs. This bit select is now wrapped in a
asSInt cast if the original rhs was an SInt so that is has the correct type.

Fixes #173

Wrap bit select generated when fixing static shift right of amount greater
than the argument width with cast to SInt if the original argument is an
SInt

Fixes #169

Transforms are new unit of modularity within the compiler.

Add unit tests for splitting expressions and padding widths

RemoveValidIf, SplitExpressions, and PadWidths

This is to start moving stuff out of Emitter and into separate passes

Changed initialization to assign the correct number of random bits.

Fixes #133

Fixes #113 and Fixes #150

Make EmptyExpression part of WIR

Change Field from IsDeclaration to HasName

Make WDefInstance an IsDeclaration