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  1. Jul 14, 2020
  3. Jul 11, 2020
  5. Jul 10, 2020
  7. Jul 09, 2020
    • Kevin Laeufer's avatar
      dedup: use structural sha256 hash instead of agnostify and serialize (#1731) · 3fee5f87
      Kevin Laeufer authored 
      

* benchmark: add hot.DedupBenchmark

* dedup: use structural md5 hash instead of agnostify and serialize

* StructuralHash: generate PrimOp LUT

* StructuralHash: change MessageDigestHasher to not be a case class

* StructuralHash: we want Blocks and EmptyStmt to be ignored

* StructuralHash: use SHA-256 instead of MD5

* StructuralHash: clarify extmodule port name agnistification

* StructuralHash: hash the name of width vars instead of trying to agnostify

This should be in line with the old Dedup behavior.
The prior use of n(..) was incorrect since the namespace
of these vars is different from the normal module scope namespace.

* StructuralHash: address Schuyler's review comments

Co-authored-by: default avatarmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
      3fee5f87
    • Kevin Laeufer's avatar
      ir: add faster serializer (#1694) · 05ba1c9d
      Kevin Laeufer authored 
      

This Serializer which is implemented
external to the IR node definition
uses a StringBuilder to achieve about a
1.7x performance improvement when serializing.

Eventually, all implementations of the
`serialize` methd should be replaced with
a call to `Serializer.serialize`.

However, for this PR we keep the old
code in place in order to allow for easy
regression testing with the benchmark JAR
like this:
> java -cp utils/bin/firrtl-benchmark.jar \
  firrtl.benchmark.hot.SerializationBenchmark \
  ~/benchmarks/medium.pb 2 5 test

Co-authored-by: default avatarmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
      05ba1c9d
  9. Jul 08, 2020
  11. Jul 02, 2020
  13. Jun 27, 2020
  15. Jun 26, 2020
  17. Jun 25, 2020
  19. Jun 24, 2020
    • Jack Koenig's avatar
      Don't Dedup modules if it would change semantics (#1713) · e0e68568
      Jack Koenig authored 
      If a module has ports of type Bundle that are used in aggregate
connections in parent modules, Dedup cannot change the names of the
fields of the Bundle or it would change the semantics of the connection.
Dedup now detects this case and refrains from agnostifying the ports of
such modules to prevent this issue.
      e0e68568
    • Tom Alcorn's avatar
      Basic model checking API (#1653) · 8322316a
      Tom Alcorn authored 
      

* Add assume, assert, cover statements
* Assert submodule assumptions
* Add warning when removing verification statements
* Remove System Verilog behaviour emitter warning
* Add option to disable AssertSubmoduleAssumptions
* Document verification statements in the spec

The syntax for the new statements is

    assert(clk, cond, en, msg)
    assume(clk, cond, en, msg)
    cover(clk, cond, en, msg)

With assert as a representative example, the semantics is as follows:
`clk` is the clock, `cond` is the expression being asserted, `en` is the
enable signal (if `en` is low then the assert is not checked) and `msg`
is a string message intended to be reported as an error message by the
model checker if the assertion fails.

In the Verilog emitter, the new statements are handled by a new
`formals` map, which groups the statements by clock domain. All model
checking statements are then emitted within the context of an `ifdef
FORMAL` block, which allows model checking tools (like Symbiyosys) to
utilize the statements while keeping them out of synthesis flows.

Co-authored-by: default avatarAlbert Magyar <albert.magyar@gmail.com>
      8322316a
    • Jack Koenig's avatar
      Add support for ValidIf to ProtoBuf [de]serialization · d1db9067
      Jack Koenig authored
      d1db9067
  21. Jun 23, 2020
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