we will leave cleaning up their voluminous output for later

FileInfo is merged

Restricts annotations to be string-based (and thus less typesafe)
Makes annotations more easily serializable and interact with Chisel

* Rewrote inline xform to fix quadratic perf. bug

Turns out caching previously inlined modules is not useful

The previous algorithm in a module, would flatten an instance's children, then
flatten that instance. This caused all instances to be effectively
inlined the number of times of its depth in the instance hierarchy,
making it O(n*d*s), where n is the number of instances, and d is the depth
of the instance, and s is the number of statements in the instance.

The new algorithm directly inlines a module by keeping track of the
parents of that instance, making it constant time with the number of
instantiated instances.

* Minor style fixes

* Fixed multi wiring

* Minor style changes

* Fix wrong omitting same clocked nondirect children

* Minor style fixes

* Bugfix: removed recursive removal in infer widths

This will certainly lead to more uninferred width errors, but now widths
that were previously incorrectly inferred are now correctly uninferred.

An example is:
  reg r : UInt, clock with: (reset => (reset, UInt<2>(3)))
  node x = add(r, r)
  r <= x

Here, r's width follows the following formula, which cannot be solved:

rWidth >= max(max(rWidth, rWidth) + 1, 2)

* Added optimizations to for better width inference

Also added exceptions for uninferred widths when checking DoPrim width
legality to not trigger compiler error

* Added additional optimizations

Required for passing all chisel3 tests

Required for passing all chisel3 tests

Also added exceptions for uninferred widths when checking DoPrim width
legality to not trigger compiler error

This will certainly lead to more uninferred width errors, but now widths
that were previously incorrectly inferred are now correctly uninferred.

An example is:
  reg r : UInt, clock with: (reset => (reset, UInt<2>(3)))
  node x = add(r, r)
  r <= x

Here, r's width follows the following formula, which cannot be solved:

rWidth >= max(max(rWidth, rWidth) + 1, 2)

Added clocklist transform

getMyAnnotations now returns Seq[Annotation]
Changed test to check number of annotations is the same

Prefix temporary names with underscores so Verilator won't trace them
Use verilator argument "--trace-underscore" if you want to trace these
signals

* handle uninferred ports gracefully in RemoveCHIRRTL

memory port directions are not inferred during CInferMDir if not being used, so handle them properly in RemoveCHIRRTL

* fix CInferTypes

Replace with more sensible comment to see LICENSE rather than including the
whole license in every file

* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers
* Transforms define inputForm and outputForm
* Custom transforms can be inserted at runtime into compiler or the Driver
* Current "built-in" custom transforms handled via above mechanism
* Verilog-specific passes moved to the Verilog emitter

Add Legalize to MiddleToLowFirrtl

Makes low firrtl more like a netlist, should probably update spec

Fixes #329

Fixed Verilog emission reduce ops with efficient implementation

Change FixedPointMathSpec tests to use FlatSpec style instead of println
Remove other printlns
Remove vim comments at end of files

* Keep package name + directory structure consistent

This annoyed me so heres a PR

* fix InferReadWrite references

* delete .ConvertFixedToSInt.scala.swo

Added wiring pass and simple test

* fix imports in InferReadWrite

* improve reference & name resolution in ReplSeqMem

* add comments

While unsafe, this supports Verilog parameter types.
Tests now require Verilator 3.884+ to pass.

Adds support for Integer, Double/Real, and String parameters in external
modules. Also add name field to extmodules so that emitted name can be
different from Firrtl name. This is important because parameterized extmodules
will frequently have differing IO even though they need to be emitted as
instantiating the same Verilog module.

Change integration tests to be classes that extend abstract classes. This
allows them to be run in parallel. Also expand API to support Verilog
resources in integration tests.

* Create a simple system for executions and command line parameters
New model for tracking parameters and having those parameters
register scopt command to allow the parameters to be set by
command line args.
Create composable forms of the these parameters to allow separate
elements of the chisel3 toolchain to combine these parameters
Create execution return structures that simplify return values
to earlier toolchain elements

* just a little bit of cleanup

* Fixes for Adam's comments on PR

* knuckled under to self-pressure to allow former -i and -o to work

* knuckled under to self-pressure to allow former -i and -o to work

* show defaults for command line args with them

* A couple of fixes from merging latest master

* Implement a log4scala like logging system
This system has the rather remarkable property
that it is possible to turn it on conveniently when
you want it.  It also provides for class level granularity
as well as the traditional Error, Warn, Info, Debug

* some style fixes and change infoMode default to append per PR #328

* some style fixes and change infoMode default to append per PR #328

* support -i -o and -X
a couple of indentation and spacing fixes

* toBitMask cat direction should be consistent with data

* minor comment updates

* moved remaining mem passes/utils to memlib

* changed again so that data, mask are consistent. data element 0, bit 0 = LSB (on RHS) when concatenated

duplcate memory detection should be in circuit-level, not in module-level

Chisel now depends on Firrtl so we need to publish to run Chisel tests