Improve annotation logging

If an annotation cannot be serialized by json4s, we should not throw
exceptions when doing trace-level logging.

* RenameMap: remove implicit rename chaining

* RenameMap: remove trailing comma

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* - modify firrtlEquivalenceTest to use yosys equiv_simple/equiv_induct instead of miter
- add RemoveValidIf pass to MinimumLowFirrtlOptimization

* add EquivalenceTest to FirrtlSpec.scala, make classes in IntegrationSpec.scala abstract

* change types of inputForm/outputForm to CircuitForm

* change EquivalenceTest message

* remove ICache equivalence tests

* fix rebase errors

* Add Ops scalatests to LEC suite

* Only run compiler-path-comparison LEC tests on Ops design

* Fixup issues with merge

Co-authored-by: Albert Magyar <albert.magyar@gmail.com>

* Closes #1597

* Fixes #1561
* Add test for zero-reset reg from #1561

* Move reg/mem initializations to end of module
* Add comment before reg/mem init if inits exist

Speed up Deduplication

Speed up InferTypes and CInferTypes

Do the same in CInferTypes

Co-authored-by: Scala Steward <me@scala-steward.org>
Co-authored-by: Scala Steward <43047562+scala-steward@users.noreply.github.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: Scala Steward <me@scala-steward.org>
Co-authored-by: Scala Steward <43047562+scala-steward@users.noreply.github.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Generalize keyword collision to name manipulation, Add {Lower,Upper}CaseNames Transforms

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Adds an options to the FIRRTL compiler command line to schedule the
LowerCaseNames and UpperCaseNames transforms.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Creates the features package and populates it with two new transforms:
LowerCaseNames and UpperCaseNames. These transforms convert all names
in a FIRRTL circuit to lower case or upper case. This is intended to
help align generated Verilog with the policies of the
company/institution using it.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

squash! Add LowerCaseNames and UpperCaseNames transforms

Generalize the operations of the RemoveKeywordCollisions transform
into a new ManipulateNames transform. The ManipulateNames transform is
an abstract transform for making conditional modifications to
keywords/names in a FIRRTL circuit.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Labeling a PR with Milestone 1.2.X now will tell Mergify to backport it
to both 1.2.x and 1.3.x.

Co-authored-by: Albert Magyar <albert.magyar@gmail.com>

Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>

* consolidated wire <type> x; assign x = y; to wire <type> x = y;

* Remove dead code from Emitter.scala

Co-authored-by: Albert Magyar <albert.magyar@gmail.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Bugfix - have AppendInfo use MultiInfo, rather than appending with :

* Address reviewer feedback

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Constant Prop Reduction Operations of Literals

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Speed up CheckHighForm

Expression Types are derived. They cannot cause the errors detected by
CheckHighFormLike independently of the user-specified types that remain
chedked. This speeds up CheckChirrtl and CheckHighForm substantially.

Don't serialize Expressions unless there is an error