- Mar 21, 2019
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Edward Wang authored
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- Mar 20, 2019
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Edward Wang authored
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Jack Koenig authored
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Jack Koenig authored
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Jack Koenig authored
This caused Ammonite to crash
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Jim Lawson authored
If we use the same root directory for antlr and protobuf generated files, we get errors in docJar() when we compile the same files twice. Use a distinct sub-directory of dest for each suite of generated files. While we're here, make 2.12.4 the default Scala version and bump the antlr runtime to 4.7.1
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Jim Lawson authored
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Jim Lawson authored
Cleanup;provide runtime exception if no schemas.
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Jim Lawson authored
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Jim Lawson authored
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Jim Lawson authored
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Jim Lawson authored
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John Wright authored
Designs with no SeqMems should produce empty MemConf strings, and this should be parsable without excepting (#1060)
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- Mar 19, 2019
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Jim Lawson authored
* Add serialization support for LoadMemoryFileType in LoadMemoryAnnotation Add custom LoadMemoryFileTypeSerializer. Add test to verify LoadMemoryAnnotation can be correctly serialized/deserialized. * Simplify and focus LoadMemoryAnnotation serialization/deserialization. Respond to comments on earlier implementations. * Add type FileType definition for current chisel3 code.
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- Mar 08, 2019
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John Wright authored
* Copy MemConf.scala from ucb-bar/barstools#35 into memlib. This provides a data structure wrapper around the existing memory conf format which contains both reading and writing methods, making it easier to write code that needs to read the format. * Add MemConf tests and use a Map[MemPort, Int] for port lists instead of a Seq[MemPort] which is a bit less fragile.
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- Mar 06, 2019
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Jean Bruant authored
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- Mar 01, 2019
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Adam Izraelevitz authored
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Albert Magyar authored
* Don't create nodes to hold Muxes with >0 void cases * Added test case demonstrating void error * Memoize intermediate expression when checking for WVoid-ness
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- Feb 28, 2019
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Jim Lawson authored
* Add --nodedup option to facilitate FIRRTL to verilog regression testing. * Short-circuit the DedupModules transform if NoCircuitDedupAnnotation exists.
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- Feb 27, 2019
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Chick Markley authored
* Create a simple generic graphviz renderer for DiGraph There are three basic kinds - A simple default renderer - A ranked renderer that places nodes in columns based on depth from sources - A sub-graph render for graphs that contain a loop - Renders just nodes that are part of first loop found - Plus the neighbors of the loop - Loop edges are shown in red. * Create a simple generic graphviz renderer for DiGraph - Moved the graph loop finder into DiGraph - Fixed scala doc per Edward's comments
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- Feb 26, 2019
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Jack Koenig authored
* Run CheckHighForm after all non-emitter transforms in firrtl tests * Remove shlw from checks.scala * Removed mistake in fix * Fix FirrtlSpec fix
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Albert Magyar authored
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- Feb 25, 2019
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Schuyler Eldridge authored
Fix almost all scaladoc warnings, add source links
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Schuyler Eldridge authored
Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Schuyler Eldridge authored
This fixes all Scaladoc warnings except for those trying to link to Java. Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- Feb 23, 2019
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Albert Chen authored
* refactor InferWidths to allow for extra contraints, add InferWidthsWithAnnos * add test cases * add ResolvedAnnotationPaths trait to InferWidthsWithAnnos * remove println * cleanup tests * remove extraneous constraints * use foreachStmt instead of mapStmt * remove support for aggregates * fold InferWidthsWithAnnos into InferWidths * throw exception if ref not found, check for annos before AST walk
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Jack Koenig authored
Instead, just forward the exception
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Adam Izraelevitz authored
Previously would require all requested reviewers must have approved a PR before merging.
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- Feb 22, 2019
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Adam Izraelevitz authored
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Jim Lawson authored
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Jim Lawson authored
* No time left for you - quickly rename deep bundles still occasionally fails. Run the "quick" calibration test three times and choose the maximum as the basis for comparison with the "deep" test. * Rename local variable to less confusing name.
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Adam Izraelevitz authored
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Adam Izraelevitz authored
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Schuyler Eldridge authored
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Nick Hynes authored
* Correctly handle dots in loaded memory paths * Added test for loadmem filename
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- Feb 21, 2019
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Jim Lawson authored
* Attempt to deal with timing vagaries in UniquifySpec.quicklyrenamedeepbundles Switching to Scala 2.12.8 cause this test to start failing on OSX. Try earlier scheme to compare shallow vs deep to reduce brittleness. * Address review concerns; update comment.
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- Feb 15, 2019
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Jack Koenig authored
Fixes #219 * Adds AsyncResetType (similar to ClockType) * Registers with reset signal of type AsyncResetType are async reset registers * Registers with async reset can only be reset to literal values * Add initialization logic for async reset registers
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- Feb 12, 2019
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John Wright authored
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- Feb 06, 2019
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Schuyler Eldridge authored
Add "mverilog" Compiler Option, MinimumVerilogEmitter
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Schuyler Eldridge authored
This uses the foldShiftRight method of the ConstantPropagation Transform when legalizing Shr PrimOps. This has the effect of removing literals with bit extracts from the MinimumVerilogCompiler. This makes the formerly private foldShiftRight method of a public method of the ConstantPropagation companion object. Tests in the MimimumVerilogCompilerSpec are updated to check that Shr is handled as intended. Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
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