Commits · partition-circuit · github.com / freechipsproject / firrtl

Feb 13, 2020

Create PartitionCircuit transform for minimizing test cases · a918f97b
Jack Koenig authored Feb 12, 2020

a918f97b
Merge pull request #1388 from freechipsproject/allow-self-renames · dd6bbd4f
Schuyler Eldridge authored Feb 12, 2020
```
Allow self renames
```
dd6bbd4f
Add test of RenameMap not recording same rename · 1909e216
Schuyler Eldridge authored Feb 12, 2020
```
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
```
1909e216
Add test of RenameMap self-renaming · 00e736fb
Schuyler Eldridge authored Feb 12, 2020
```
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
```
00e736fb
Update RenameMap Scaladoc for self-rename, distinc · 94c84eb1
Schuyler Eldridge authored Feb 12, 2020
```
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
```
94c84eb1

Record self-renames in RenameMap, distinct renames · 6426b4af

Schuyler Eldridge authored Feb 12, 2020



Change the behavior of RenameMap.completeTarget so that self-renames
do not silently *not* happen. Previously, requests to self-rename
would be ignored unless they were packaged in a sequences of renames
that included a self-rename.

Change renames to be recorded distinctly so that multiple requests to
rename to the same thing will now deduplicate. Previously, these
renames would be recorded multiple times. This change was required
because allowing self-renames exposed a bug in InferWidthsAnnosSpec
due to multiple renames.

These changes benefit the situation where you rightly want to do a
self-rename. Namely, when doing module duplication (with the
EliminateTargetPaths transform).

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Do not record the same rename multiple times

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

6426b4af

Repl seq mem renaming (#1286) · eabc3855

Jack Koenig authored Feb 12, 2020



* Consume NoDedupMemAnnotations in ResolveMemoryReference

The ComponentName being pointed to by the annotation no longer exists
after ReplaceSeqMems so we should consume the annotations

* Support renaming in ReplaceMemMacros

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

eabc3855

Update sbt-unidoc to 0.4.3 (#1345) · f4645fe6
Scala Steward authored Feb 12, 2020
```
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
```
f4645fe6
Update sbt-antlr4 to 0.8.2 (#1331) · 8e420a46
Scala Steward authored Feb 12, 2020
```
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
```
8e420a46

Feb 12, 2020

Merge pull request #1387 from freechipsproject/InstanceGraph.staticInstanceCount-fix · a4000ad7
Schuyler Eldridge authored Feb 11, 2020
```
Include Dead Modules in InstanceGraph.staticInstanceCount
```
a4000ad7
Add InstanceGraph.staticInstanceCount tests · ba28e5d9
Schuyler Eldridge authored Feb 11, 2020
```
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
```
ba28e5d9

Report dead modules in staticInstanceCount · 55cb667f

Schuyler Eldridge authored Feb 11, 2020

Change InstanceGraph.staticInstanceCount to include modules with no
instances. Previously, these modules would just not be included.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

55cb667f

Removed unused imports in src/test/ (#1381) · 08184885
Jim Lawson authored Feb 11, 2020
```
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
```
08184885

Update sbt to 1.3.8 (#1354) · 34681182

Scala Steward authored Feb 12, 2020



Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

34681182

Fixing lint error: x + -1 (#1374) · ce056037

Adam Izraelevitz authored Feb 11, 2020



* Generates lint-clean Verilog for the case: x + -1

...where x is anything and 1 is any literal.

Master behavior:

  input x : SInt<8>
  output z : SInt<9>
  z <= add(x, SInt(-2))

generates

  assign z = $signed(x) + -8'sh2;

After this PR:

  assign z = $signed(x) - 8'sh2;

If the literal is the maximum possible literal, a special case is triggered to properly trim the resulting subtraction.

Input:

  input x : SInt<2>
  output z : SInt<3>
  z <= add(x, SInt(-2))

now generates (after this PR)

  assign z = $signed(x) - 3'sh2;

* Updated documentation

* Change ArrayBuffer to ListBuffer

* Change name to minNegValue

* Remove mutable public interfaces

Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

ce056037

Update scalacheck to 1.14.3 (#1336) · db9a16db

Scala Steward authored Feb 12, 2020



Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

db9a16db

Update sbt-scoverage to 1.6.1 (#1335) · 357ec734

Scala Steward authored Feb 12, 2020



Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

357ec734

Support MemConfs with very deep memories (#1367) · 668db17e
Jerry Zhao authored Feb 11, 2020
```
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
```
668db17e

Add reviewer checklist / update contributor checklist (#1375) · 1937cfd5

Adam Izraelevitz authored Feb 11, 2020



* Add reviewer checklist / update contributor checklist

* Update PULL_REQUEST_TEMPLATE.md

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

1937cfd5

Update commons-text to 1.8 (#1333) · 4531a8ff

Scala Steward authored Feb 12, 2020



Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

4531a8ff

Update junit to 4.13 (#1332) · 386c2fef

Scala Steward authored Feb 12, 2020



Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

386c2fef

Update protoc-jar to 3.11.1 (#1330) · 85524c50

Scala Steward authored Feb 12, 2020



Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

85524c50

Update sbt-unidoc to 0.4.2 (#1329) · bc281b07

Scala Steward authored Feb 11, 2020



Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

bc281b07

Update sbt-buildinfo to 0.9.0 (#1328) · 9c128fc2

Scala Steward authored Feb 11, 2020



Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

9c128fc2

Update sbt-assembly to 0.14.10 (#1327) · 48cbe682
Scala Steward authored Feb 11, 2020
```
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
```
48cbe682
Update sbt-scalafix to 0.9.11 (#1326) · ad3d4ac2
Scala Steward authored Feb 11, 2020
```
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
```
ad3d4ac2

Feb 11, 2020

[spec] Change sub(UInt, UInt) output type to UInt (#1378) · c1738a1b
Albert Magyar authored Feb 10, 2020

c1738a1b
Merge pull request #1370 from freechipsproject/issue-1309 · 1b475c42
Schuyler Eldridge authored Feb 10, 2020
```
Rename Modules Duplicated by EliminateTargetPaths
```
1b475c42

Test EliminateTargetPaths ModuleTarget anno duping · bcbe60de

Schuyler Eldridge authored Feb 07, 2020



Add a test that EliminateTargetPaths properly duplicates an annotation
pointing at a ModuleTarget.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

bcbe60de

Rename modules when duplicating instances · 64762d2e

Schuyler Eldridge authored Feb 07, 2020



Change the behavior of EliminateTargetPaths to generate ModuleTarget
renames when instances are duplicated. Previously, only InstanceTarget
renames would be generated.

In effect, annotations targeting a duplicated module when be
duplicated to point at the original and duplicated module.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

64762d2e

Add Target utility referringModule · 72427067

Schuyler Eldridge authored Feb 07, 2020

This adds a utility method, referringModule, to the Target object that
behaves like IsMember.pathlessTarget except that it returns the module
of an InstanceTarget. This is useful for situations where you want to
get at "the module" a target is pointing at, but you want behavior
to get an actual module from an instance.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

72427067

Feb 08, 2020
- Merge pull request #1366 from freechipsproject/dueling-const-prop · dc9709c5
  Albert Magyar authored Feb 07, 2020
```
Better register const prop through speculative de-optimization
```
  dc9709c5
Feb 07, 2020
- Add extra 'de-optimization' opportunity for register const prop test · ec365cec
  Albert Magyar authored Feb 07, 2020
  
  ec365cec
- Refactor handling of reg const prop entries to cover more cases · 71240a3c
  Albert Magyar authored Feb 07, 2020
  
  71240a3c
- Better register const prop through speculative de-optimization · 98a23c0c
  Albert Magyar authored Feb 06, 2020
```
* Fixes #1240
* Add failing reg const prop test case from #1240
```
  98a23c0c
- Add constant prop to async regs (#1355) · b36e36d9
  Adam Izraelevitz authored Feb 06, 2020
```
* Add constant prop to async regs

* Added another test of no reset value but constant assignment

* Clarify name of updateNodeMap

* Update constant assignment of async reset to not be inferred as a latch, works with donttouch

* Revert "Update constant assignment of async reset to not be inferred as a latch, works with donttouch"

This reverts commit 952bf381.
```
  b36e36d9
Feb 06, 2020
- Merge pull request #1362 from freechipsproject/andr-reduction-base-case · 39f8563c
  Schuyler Eldridge authored Feb 06, 2020
```
Change zero-width base case for Andr
```
  39f8563c
- Add note to spec about reductions on zero-width wires · 7e3a4240
  Albert Magyar authored Feb 06, 2020
  
  7e3a4240
- [Behavior change] Andr of zero-width wire now returns UIntLiteral(1) · c9aff1ca
  Albert Magyar authored Feb 06, 2020
```
* Fixes #1344
```
  c9aff1ca
- Emit 'else' case for trivial-valued async reset regs to avoid latches (#1359) · bf0ea927
  Albert Magyar authored Feb 05, 2020
  
  bf0ea927