Also add support for width inference

This comment causes vcs to treat this as a spare memory,
so it will dynamically allocate the required memory, and can
support very large reg constructs this way. This is useful for
test bench memories that might be simulating back DRAM or the like.

* Rework Attach to work on arbitrary Analog hierarchies

If there are zero or one Analog sources in an Attach (source meaning
wire or parent module port), then the Attach will be emitted as a simple
point to point connection. In the general case, alias is used for
simulation while forwards and backwards assigns for synthesis. Verilator
does not currently support the general case so an `ifdef Verilator
`error is emitted.

* Add helper functions for creating WRef from Reg and Wire

This fixes an issue I was having with my ClockListAnnotations being duplicated.

h/t @azidar

Fixes ucb-bar/chisel3#420

* fixed up impementation of deleteDirectoryHierarchy
Added a few more tests

* Round 2 of moving verilog to target dir
Only create .f file if some files have been moved
Some small style fixes in Driver
Restored lost functionality to add -f argument in verilogToCpp
Fixed loadAnnotations to add targetDir regardless of annotations arriving from file or through options

This is similar to pr #392 - fetch the resource as a resource, not as a random file otherwise the test will fail if it is executed anywhere outside of the actual source directory.

Will place tests in ./test_run_dir/ instead of /tmp/

* First pass at implementing a annotation based mechanism to move black box verilator files into the target directory

* A little bit of style cleanup

* A little bit of style cleanup

* Fix the driver, wasn't appending targetDir properly
Add some docs

* test had wrong value now that targetdir is added to annnos

* Now saves a list of all black box verilog files moved into target directory.
Then creates a file black_box_verilog_files.f that contains this list with -v prepended to each line

* Made black box source helper be low to low form
Added it to the verilog compiler transforms
Added a test to make sure it got there

* targetDir annotation is targeted to a CircuitName("All")

* type conversions between sint/fixed and uint added at memory interfaces for replseqmem

* turns out asFixed requires bp as constant in PrimOps (really should be documented)

* fixed legalizeconnects to handle FixedPt

* added tests for replseqmem failure with signed types

* Move BackendCompilationUtilities into a util package for use by chisel3.
Some of this could be moved into a more general tools package, but since chisel3 already has a dependency on firrtl ...

* Push util down into firrtl so as not to conflict with scala.util.

Add FixedType to uniqueify match statement.

Add a test for cmem and smem with fixed point numbers

Fix ScalaDoc complaints; add sbt-site, sbt-ghpages boilerplate.

Add support for top-level use of MiddleFirrtlCompiler.

* Add pass that fixes up widths with modulus operator for verilog

* Add basic test for Verilog emission of Rem

* Oops, left in some printlns.

Also base max dshl check on MaxWidth instead of just 31 bits
Resolves #320

Also, delete run regression part of Installation since `sbt test` does that anyway

If we execute tests somewhere other than the root of the firrtl project directory (in a parent project directory for examples), the resource file may not be where we expect it.
Also clean up imports.

* Rename implict module "clk" input to "clock".
This doesn't rename all the "self-contained" test instances.
nor the memory "clk" enables,
nor the implict module "clk"s in the regress .fir files.

* Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances.
This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.