Verification statements are guarded by reset.
If this reset happens to be a "preset" type
reset, they should always be active.
The easiest way to achieve that is to replace
all uses of "preset" resets with zero.

This fixes an off by one error, where 3 was erroneously
accepted as in-bounds for a memory of depth=3

* Enable CI for 1.5.x branch
* Enable Mergify for 1.5.x branch
* Drop 1.2.x from Mergify

* Add FileInfo to asyncResetAlwaysBlocks

Always blocks need three FileInfo (if, true, false) to show line numbers,
but initially, every always blocks only have one FileInfo (false).

RemoveReset adds the extra two FileInfo to sync always blocks,
so sync always blocks can have line numbers.

Async always blocks don't provide their only FileInfo, so there are no line numbers.

This commit gives async always block the extra FileInfo to show line numbers for them.

This code:

```scala
import chisel3._
import chisel3.stage._
import firrtl.CustomDefaultRegisterEmission

class Test extends Module with RequireAsyncReset {
  val io = IO(new Bundle {
    val in = Input(Bool())
    val out = Output(Bool())
  })
  val valid = RegInit(false.B)
  valid := io.in
  io.out := valid
}

object Test extends App {
  new ChiselStage().execute(Array(), Seq(
    ChiselGeneratorAnnotation(() => new Test()),
    CustomDefaultRegisterEmission(useInitAsPreset = false, disableRandomization = true)
  ))
}
```

will generate this Verilog:

```verilog
module Test(
  input   clock,
  input   reset,
  input   io_in,
  output  io_out
);
  reg  valid; // @[Playground.scala 10:22]
  assign io_out = valid; // @[Playground.scala 12:10]
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[Playground.scala 10:22]
      valid <= 1'h0; // @[Playground.scala 10:22]
    end else begin
      valid <= io_in; // @[Playground.scala 11:9]
    end
  end
endmodule
```

they have correct line numbers (10, 10, 11).

* Add test for async always block line numbers

* Add comment for review

* Fix unreachable code warning by changing match order

Simulation Statements did not previously extend IsDeclaration, but now
they do so their match blocks need to be above IsDeclaration.

* Handle MemoryNoInit case in RtlilEmitter

* Remove use of deprecated logToFile

* Fix uses of LegalizeClocksTransform

Replaced all uses of LegalizeClocksTransform with
LegalizeClocksAndAsyncResetsTransform.

* Remove use of CircuitForm in ZeroWidth

Fix bugs related to arithmetic ops inlined into a mux leg.  Add formal
equivalence checks to lock in this behavior.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This should fix issue #2436

* Add renamemap.MutableRenameMap which includes these methods without
  deprecation
* Deprecate Stringly typed RenameMap APIs which were accidentally
  undeprecated a while ago

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Change AnnotationSeq underlying from List to Seq

It was nothing but pointless copying.

* Make propagateAnnotations faster

There was lots of expensive logic for very little benefit.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

1. Add CustomRadix{Def,Apply}Annotation to define and apply custom radix.
2. Add CustomRadixConfigFileAnnotation to output a JSON config file so
   users can generate scripts on their own.

Reviewed-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: sinofp <sinofp@tuta.io>

Improve ANTLR Parser

The ANTLR-generated concrete syntax tree (CST) takes up much more memory
than the parsed .fir file. By using a Listener, we can construct the
FIRRTL AST live with CST construction and null out the CST as we consume
pieces of it. Not only does this improve performance, it drastically
reduces max memory use for the parser.

Tweak the grammar to handle references without left-recursion. Also
split references and subreferences out from the regular expression rule
to make their parsing more efficient.

The classes should not really be part of the firrtl public API to begin
with and they cause issues during ScalaDoc generation.

Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Also remove all related APIs:

ComposableOptions
HasParser
CommonOptions
HasCommonOptions
FirrtlExecutionOptions
HasFirrtlOptions
FirrtlExecutionResult
FirrtlExecutionSuccess
FirrtlExecutionFailure
ExecutionOptionsManager
firrtl.stage.DriverCompatibility.firrtlResultView
logger.Logger.makeScope
OutputConfig
SingleFile
OneFilePerModule

* Change default LogLevel to None which means "unset"

Logger.getGlobalLevel then returns LogLevel.Warn when the current value
is LogLevel.None. This preserves the behavior of the default being
"Warn" but now uses LogLevel.None to indicate "I'm not setting the
value." This resolves issues where it was not possible to tell if
annotations were actually setting the log level or if the default level
of warn was just being filled in.

Co-authored-by: sinofp <sinofp@tuta.io>
Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: sinofp <sinofp@tuta.io>