- enables sbt plugin for scalafmt in sbt
- adds travis test requiring scalafmt for PR
- formats everything in src/
- formats build.sbt

* Use signed output in LargeParamExecutionTest

Change the Verilog used in LargeParamExecutionTest to match its
ExtModule specification. An ExtModule with an SInt port should map to
a separate Verilog module with a signed port and this is disjoint from
an ExtModule with a UInt port.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Error on ExtModules w/ same defname, diff. ports

Adds a high form check to ensure that external modules that have the
same defname also have exactly the same ports.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: chick <chick@qrhino.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Avoid repeated inlining in FlattenRegUpdate

When-else structure can lead to the same complex mux structure being
the default on several branches in register update logic. When these are
inlined, it can lead to artifical unreachable branches that show up as
coverage holes in coverage of the emitted Verilog. This commit changes
the inlining logic to prevent inlining any reference expression that
shows up multiple times because this is a common indicator of the
problematic case.

* Add tests for improved register update logic emission

* Improve FlattenRegUpdate comment and add more tests

* [skip formal checks] ICache equivalence check verified locally

They are never used outside of the class
not even in tests.

* WIP Commit

* Add EdgeDataDiGraph with views to amortize graph construction

* WIP, got basic structure, need tests to pipeclean

* First tests pass. Need more.

* Tests pass, more need to be written

* More tests pass! Things should work, except for memories

* Added clearPrev to fix digraph uses where caching prev breaks

* Removed old Component. Documented IRLookup

* Added comments. Make prev arg to getEdges

* WIP: Refactoring for CircuitGraph

* Refactored into CircuitGraph. Can do topological module analysis

* Removed old versions

* Added support for memories

* Added cached test

* More stufffff

* Added implicit caching of connectivity

* Added tests for IRLookup, and others

* Many major changes.

Replaced CircuitGraph as ConnectionGraph
Added CircuitGraph to be top-level user-facing object
ConnectionGraph now automatically shortcuts getEdges
ConnectionGraph overwrites BFS as PriorityBFS
Added leafModule to Target
Added lookup by kind to IRLookup
Added more tests

* Reordered stuff in ConnectionGraph

* Made path work with deep hierarchies. Added PML for IllegalClockCrossings

* Made pathsInDAG work with current shortcut semantics

* Bugfix: check pathless targets when shortcutting paths

* Added documentation/licenses

* Removed UnnamedToken and related functionality

* Added documentation of ConnectionGraph

* Added back topo, needed for correct solving of intermediate modules

* Bugfix. Cache intermediate clockSources from same BFS with same root, but not BFS with different root

* Added literal/invalid clock source, and unknown top for getclocksource

* Bugfix for clocks in bundles

* Add CompleteTargetSerializer and test

* remove ClockFinder, be able to compile.

* test is able to compile, but need to fix.

* public and abstract DiGraph, remove DiGraphLike.

* revert some DiGraph code, ConnectionGraphSpec passed.

* CircuitGraphSpec passed.

* minimize diff between master

* codes clean up

* override linearize and revert DiGraph

* keep DiGraph unchanged.

* make ci happy again.

* codes clean up.

* bug fix for rebase

* remove wir

* make scaladoc happy again.

* update for review.

* add some documentation.

* remove tag

* wip IRLookup

* code clean up and add some doucmentations.

* IRLookup cache with ModuleTarget guarded.

* make unidoc and 2.13 happy

Co-authored-by: Adam Izraelevitz <azidar@gmail.com>
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

* ir: use Serializer.serialize where possible

* ir.Serializer: serialize MultiInfo correctly

* ir.Serializer: empty body needs to result in a skip statement

The firrtl grammar requires at least one statement.

* ir.Serializer: correctly serialize fixed point types and literals

* Serializer: change Seq -> Iterable in order to be Scala 2.13 compatible

Scala 2.13 support

0.9.16+ fixes https://github.com/scalacenter/scalafix/issues/1109
-Ywarn-unused-imports seems to be no longer supported by 2.13:
https://github.com/scala/scala/releases/tag/v2.13.0

This should not be needed in firrtl.

The values end up being converted to BigDecimal
anyways.

Extending HashMap is discouraged.

semanticdb seemed to be missing a 2.13 package

* WiringUtils.sinksToSources: make sinkInsts order deterministic

* WiringUtils: make owners a LinkedHashMap

* Wiring: only make something a Wire if it isn't a port already

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* InferTypesFlowsAndKindsSpec: test the results of InferTypes, ResolveKinds and ResolveFlows

* Don't use passes sub-package in tests

This changes two test files using the "passes" sub-package to
"firrtl.passes". This allows a new "firrtlTests.passes" package to be
freely created and used without a name collision.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* ResolveFlows: only depends on types and working ir

The types are needed to know the orientation of
a bundle field of a SubField node.

* InferTypes: fix bugs with unknown widths on ports and memories

* LoweringCompileSpec: Uniquify pass moved

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* RenameMapSpec: try rename instance and port

* RenameMapSpec: explicit chaining is required

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

dshl amount must be < 20 bits, not <= 20 bits.

Resolves #1794

Create new scopes for child statements of Conditionally

* See #1505
* Inferred mports are implicitly added to scope of their parent mem
* This allows current chisel3 emission to work with new scope checks
* This may change in a future refactor of CHIRRTL memory ports

* Add specific test for shadowing

* Fixes #1505

* See freechipsproject/chisel3#1408

Add a Treadle build to the portion of CI that runs Chisel3 tests.
Chisel3 needs to have a master copy of Treadle in order for it to
work and cannot rely on resolution from Maven.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Move new transforms, recently added, into existing or new sets of
transforms (defined in firrtl.stage.Forms).

One transform is a mandatory low FIRRTL optimization:

  - firrtl.transforms.LegalizeAndReductionsTransform

Previously, this was included as a prerequisite of all Verilog
emitters (minimum, normal, and SystemVerilog).

Two transforms associated with converting and removing the new
verification statements are moved into a new set of transforms,
AssertsRemoved:

  - firrtl.transforms.formal.ConvertAsserts
  - firrtl.transforms.formal.RemoveVerificationStatements

Previously, these transforms were directly added as prerequisites to
the minimum Verilog and normal Verilog emitter, but not the
SystemVerilog emitter.

The designation of inputForm=LowForm for legacy, custom transforms is
updated to include assertion removal transforms as part of their
optionalPrerequisites. This has the effect of continuing to cause
inputForm=LowForm transforms to run as late as possible (right before
the low FIRRTL, minimum Verilog, Verilog, or SystemVeriog emitter).

Tests are updated to reflect the new order in both CustomTransformSpec
and LoweringCompilersSpec.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* add sign-extend const-prop test

* Emitter: don't wrap Neg operand in concat