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  1. Apr 06, 2022
  3. Mar 03, 2022
  5. Jan 27, 2022
    • mergify[bot]'s avatar
      Fix faulty MemorySynthInit behavior (#2468) (#2476) · 2f007ce4
      mergify[bot] authored 
      

- Fix & test MemorySynthInit behavior with MemoryArrayInitAnnotation and MemoryScalarInitAnnotation.
Add test case for MemoryRandomInitAnnotation which is, on the contrary, expected not to leak any randomization statement in synthesis context.

- Refactor MemoryInitSpec for improved results readability

Context:

PR #2166 (commit: 4530152) introduced MemorySynthInit annotation to control whether statement generated with Memory*InitAnnotation (emitted within initial begin block in verilog) should be guarded with ifndef SYNTHESIS or not.
Unfortunately only one configuration (MemoryFileInlineAnnotation) has been tested while the others have been generating incorrect verilog statements (MemoryArrayInitAnnotation and MemoryScalarInitAnnotation).

Signed-off-by: default avatarJean Bruant <jean.bruant@ovhcloud.com>
(cherry picked from commit 475c165c

)

Co-authored-by: default avatarJohn's Brew <46595442+johnsbrew@users.noreply.github.com>
      2f007ce4
  7. Jan 26, 2022
  9. Jan 20, 2022
  11. Jan 18, 2022
  13. Jan 12, 2022
  15. Jan 06, 2022
    • sinofp's avatar
      Add FileInfo to asyncResetAlwaysBlocks (#2451) · 3e494b5c
      sinofp authored 
      * Add FileInfo to asyncResetAlwaysBlocks

Always blocks need three FileInfo (if, true, false) to show line numbers,
but initially, every always blocks only have one FileInfo (false).

RemoveReset adds the extra two FileInfo to sync always blocks,
so sync always blocks can have line numbers.

Async always blocks don't provide their only FileInfo, so there are no line numbers.

This commit gives async always block the extra FileInfo to show line numbers for them.

This code:

```scala
import chisel3._
import chisel3.stage._
import firrtl.CustomDefaultRegisterEmission

class Test extends Module with RequireAsyncReset {
  val io = IO(new Bundle {
    val in = Input(Bool())
    val out = Output(Bool())
  })
  val valid = RegInit(false.B)
  valid := io.in
  io.out := valid
}

object Test extends App {
  new ChiselStage().execute(Array(), Seq(
    ChiselGeneratorAnnotation(() => new Test()),
    CustomDefaultRegisterEmission(useInitAsPreset = false, disableRandomization = true)
  ))
}
```

will generate this Verilog:

```verilog
module Test(
  input   clock,
  input   reset,
  input   io_in,
  output  io_out
);
  reg  valid; // @[Playground.scala 10:22]
  assign io_out = valid; // @[Playground.scala 12:10]
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[Playground.scala 10:22]
      valid <= 1'h0; // @[Playground.scala 10:22]
    end else begin
      valid <= io_in; // @[Playground.scala 11:9]
    end
  end
endmodule
```

they have correct line numbers (10, 10, 11).

* Add test for async always block line numbers

* Add comment for review
      3e494b5c
  17. Dec 28, 2021
  19. Dec 22, 2021
    • Jack Koenig's avatar
      Remove some warnings (#2448) · 4f3d1003
      Jack Koenig authored 
      * Fix unreachable code warning by changing match order

Simulation Statements did not previously extend IsDeclaration, but now
they do so their match blocks need to be above IsDeclaration.

* Handle MemoryNoInit case in RtlilEmitter

* Remove use of deprecated logToFile

* Fix uses of LegalizeClocksTransform

Replaced all uses of LegalizeClocksTransform with
LegalizeClocksAndAsyncResetsTransform.

* Remove use of CircuitForm in ZeroWidth
      4f3d1003
    • Kevin Laeufer's avatar
      smt: deal correctly with negative SInt literals (#2447) · 2d197c84
      Kevin Laeufer authored
      2d197c84
  21. Dec 18, 2021
  23. Dec 17, 2021
  25. Dec 14, 2021
  27. Dec 05, 2021
  29. Dec 02, 2021
  31. Nov 30, 2021
  33. Nov 24, 2021
  35. Nov 23, 2021