Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Adds an alternative representation of types that mimics what the MLIR
FIRRTL dialect does. Input, output, flow, and passive are all squashed
into one canonicalized representation.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Add support for instance input RHS usage replacement. Any references
like this are included in the omnibus synthetic wire.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Remove case in CheckFlows that allowed the use of a module port or
instance port sink as a source. This was never allowed in the FIRRTL
spec, but is allowed in Chisel and shows up in CHIRRTL. These types of
usages in CHIRRTL are now removed with a transform before CheckFlows
runs.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Change Utils.splitRef to use the actual IR types instead of their
WIR aliases. Update the Scaladoc note to reflect this.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

This is now set by sbt-ci-release

sbt-ci-release changes the commands required to publish to Sonatype.
While this may be a desirable change at some point, it is inconsistent
with other repos. Reverting for the time being.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* add test for RemoveAccessesSpec.

* fix nested SubAccess bug.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Add SortModules to transform to def-before-use

Adds a new transform, SortModules, that transforms a FIRRTL circuit
to enforce an invariant of modules and external modules being defined
before use. This transform is left as optional in the event that a
user may wish to have a quick way of getting the circuit to respect
this property as may be expected of some other tool, e.g., MLIR.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Add test of SortModules transform

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Verilator 4.034 was complaining about wires being named weak and strong
because those are SV 2009 keywords.  Added them to the Utils.v_keywords list

* Make MultiTargetAnnotation.targets a def

This enables the annotation writer to choose their own underlying data structure

* Update MultiTargetAnnotation ScalaDoc

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Seq[(Int, DoPrimGen)] to Map[ExprGen[_ <: Expression], Int]

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Uses sbt-ci-release for automation

It would replace them with a validif node with a UIntLiteral which can
lead to type errors.

* smt: add test for write port collision

* smt: add missing call to insertDummyAssignsForMemoryOutputs

* smt: fix typo in write port code

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* split big Emitter to submodules.

* fix all deprecated warning.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* smt: add tests for assert name clashes

* smt: ensure unique signal names with a namespace

this fixes issues #1934

Fix verilog prep

* Make Stage.run protected

Change the access modifier of Stage.run from no modifier to protected.
This method is really an internal API that the user implements with
the main entry point for a Stage being "execute" or "transform". By
allowing users to access "run" they can bypass checks, mandatory file
reads/writes, and wrappers.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Make FirrtlStage.run protected

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Fix "fix" for negative literals > 32 bits