- Oct 06, 2020
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Schuyler Eldridge authored
Change EmittedAnnotation from a NoTargetAnnotation to a SingleTargetAnnotation. Concretely, this means that some string that the emitter produces, be it a Verilog or FIRRTL IR string, is now associated with a specific circuit "thing". This has the benefit of allowing for transforms that run after an emitter to know which emitted annotation is associated with a specific component. Signed-off-by:Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Jack Koenig authored
Fix "fix" for negative literals > 32 bits
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- Oct 02, 2020
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Jack Koenig authored
Overflow of 32-bit Int would cause any negative literal value equal to -(2^(width % 32 - 1)) where width >= 32 to be incorrectly inverted
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- Oct 01, 2020
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Albert Magyar authored
VerilogMemDelays: fix lowering of direct mem-to-mem connections
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Albert Magyar authored
* Also clean up VerilogMemDelaySpec structure
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Albert Magyar authored
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Jack Koenig authored
Also speed up common case of Array[Byte]
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- Sep 29, 2020
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Chick Markley authored
now points to apache 2.0
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- Sep 24, 2020
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Jack Koenig authored
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- Sep 17, 2020
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Chick Markley authored
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- Sep 15, 2020
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Jack Koenig authored
Both use EliminateTargetPaths to duplicate modules based on annotations. Currently, EliminateTargetPaths API is a little too limited so it duplicates more than it should which effectively breaks Dedup whenever DontTouchAnnotations are present. Also, make ConstProp and DCE treat all HasDontTouches as local annotations even if they are instance annotations. This is more conservative but it is generally better to preserve deduplication than to maximally optimize every instance. Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Schuyler Eldridge authored
Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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- Sep 11, 2020
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Albert Magyar authored
Specify appropriate Chisel and Treadle branches for CI tests
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Albert Magyar authored
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- Sep 10, 2020
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Jack Koenig authored
These options are generally specific to a stage and thus should not be propagating across serialization
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Albert Chen authored
* test multiinfo comparison and mux cond inlining * loosen inlining conditions * fix typo * include dshlw * fix test
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- Sep 07, 2020
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Jack Koenig authored
Also rename --Wno-scala-version-warning to --warn:no-scala-version-deprecation and adopt naming convention where resulting annotation matches the CLI option
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- Sep 06, 2020
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Jack Koenig authored
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- Sep 05, 2020
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Jack Koenig authored
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Albert Magyar authored
Legalize mem port clocks to avoid Verilator-unfriendly sensitivity lists
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Albert Magyar authored
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Albert Magyar authored
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- Sep 02, 2020
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Albert Chen authored
* InlineBooleanExpressions: test DontTouch * run scalafmt
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- Sep 01, 2020
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Jiuyang Liu authored
Make mill compatiable to 2.13.
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Jiuyang liu authored
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Albert Chen authored
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- Aug 29, 2020
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Albert Magyar authored
Restrict boolean inlining to avoid context-sensitive width bugs
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Albert Magyar authored
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Albert Magyar authored
* Restore depth-agnostic inlining for simple 'lhs = ref' bool assignments * Address review comments * Run scalafmt
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Albert Magyar authored
Add custom transforms 'upstream' of emitter annotation in equiv tests
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Albert Magyar authored
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Kevin Laeufer authored
* FlattenSpec: flattening a module with no instaces should be a no-op * Fix problem when flattening/inlining a lone module Fix an edge case bug in InlineInstances where a circuit containing a lone module is flattened/inlined. This now properly special cases the situation of an empty indexMap which before had to be of length >= 1. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> * Simplify rename logic in InlineInstances Co-authored-by:
Jack Koenig <koenig@sifive.com> Co-authored-by:
Albert Magyar <albert.magyar@gmail.com> Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> * Mea culpa Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by:
Jack Koenig <koenig@sifive.com> Co-authored-by:
Albert Magyar <albert.magyar@gmail.com>
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Jiuyang Liu authored
Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Schuyler Eldridge authored
* CompilerAnnotation$ emits RunFirrtlTransform Change the CompilerAnnotation object to emit RunFirrtlTransformAnnotations containing the associated emitter. This requires a fix in the Driver compatibility layer to know how to enable one-file-per module emission if either a CompilerAnnotation or a RunFirrtlTransformAnnotation(_: Emitter) is present. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> * Add ConvertCompilerAnnotation phase Add a phase, ConvertCompilerAnnotation, that converts a CompilerAnnotation to a RunFirrtlTransformAnnotation. This provides a warning to the user if this path is taken. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> * Add test of ConvertCompilerAnnotation Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> * Deprecate CompilerAnnotation$, move helper methods Deprecate the CompilerAnnotation companion object and move it's private utility inside the RunFirrtlTransformAnnotation companion object. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> * Make ConvertCompilerAnnotations private[firrtl] Make this phase private to avoid adding a deprecation warning. Also, remove an unused string value. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> * Fix incorrect string in test Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> * Add test that '-X verilog', no emitter yields file Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- Aug 27, 2020
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Kevin Laeufer authored
If there is more than one clock, this will be detected and the user will be promted to run the StutteringClock transform.
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Kevin Laeufer authored
* run scalafmtAll * ci: scalafmtCheckAll to check all code instead of just the main sources
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Jack Koenig authored
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- Aug 26, 2020
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Albert Chen authored
The following conditions must be satisfied to inline: 1. has type Utils.BoolType 2. is bound to a DefNode with name starting with '_' 3. is bound to a DefNode with a source locator that points at the same file and line number. If it is a MultiInfo source locator, the set of file and line number pairs must be the same. Source locators may point to different column numbers. 4. InlineBooleanExpressionsMax has not been exceeded 5. is not a Mux Also updates the Verilog emitter to break up lines greater than 120 characters
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- Aug 25, 2020
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Jack Koenig authored
Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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- Aug 22, 2020
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David Biancolin authored
* Elide emission of literals for async reset in sensitivity lists * Deprecate LegalizeClocksTransform Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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