Add a wrapper that reports the size of the in-memory IR representation
if the log level is info or greater.  This is intended to be used to
answer rough questions of "how much work is a specific transform
doing" or "how much is a transform throwing out of the circuit".

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

With Stage/Phase, users can provide complex functionality at the phase
level rather than just the transform level. It is useful to have the
same logging information at that level. Note that this change still logs
transforms in the same way, but now the time in inclusive of annotation
renaming which can also [unfortunately] be slow.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Fixes #2173

Constant propagation of the Xor op folds `xor(a, SInt(0))` to
`asUInt(a)`. For comparison, Or folds to `asUInt(pad(a, W))`. This can
be a problem in the following case:

    circuit Foo :
      module Foo :
        input a: UInt<3>
        output b: UInt<4>
        b <= asUInt(xor(asSInt(a), SInt<4>(0)))

This would emit the assignment as `b = a` instead of the sign-extended
`b = {{1{a[2]}},a}`.

This requires adjusting the `pad(e, t)` function use in const prop,
which currently just inserts a `Pad` prim op with the requested output
type. However, the function advertises that it pads *to the width* of
the type `t`. Some of the folds rely on this and request the padding of
a SInt<N> to the width of a UInt<M>. But the current implementation then
then actually returns a `Pad` op with type UInt<M>, instead of the
SInt<M> that was requested.

Also make minor updates to CI workflow

Using Utils.indent() gives deprecation warnings to use Serializer instead. However,
the Serializer class itself doesn't provide a means to manually indent a FirrtlNode
string a certain number of times.

The indent variable, previously hardcoded to 0, is now exposed as a second parameter
for the modified serialize function, and the old serialize function just calls the
modified serialize with indents = 0 for binary compatibility

Co-authored-by: Megan Wachs <megan@sifive.com>

* bitWidth: add scaladoc

* smt: use existing bitWidth API

To maintain binary compatibility, InlineAcrossCasts is just aliases to
the now deprecated InlineCasts. We can make the binary incompatible
change of renaming the class and object for 1.5.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Add -fpga flag to enable FPGA-oriented compilation strategies (currently for memories)

* Update name of FPGA flag based on Jack's comment
* Add Scaladoc to describe what each constituent transform does
* Add SeparateWriteClocks to --target:fpga

* Address @ekiwi comments from review
* Change match cases to scalafmt-mandated lined-up style

* Update test to include both 'old' and 'new' read-under-write values

* Optionally defines read-under-write behavior for all 'undefined' memories
* Use DefaultReadFirstAnnotation to choose read-first default
* Use DefaultWriteFirstAnnotation to choose write-first default
* Seal DefaultReadUnderWriteAnnotation based on Jack's feedback

* This is enabled by adding a PassthroughSimpleSyncReadMemsAnnotation
* Can be emitted directly with new changes to the Verilog emitter
* Add some new deprecations to VerilogMemDelays
* Run scalafmt on VerilogMemDelays

* Emit readwrite ports, if applicable
* Does not change VerilogMemDelays -> no effect on default flow
* Use more single-line declare-and-assign statements for mem wires
* Update error messages for too-complex memories in VerilogEmitter
* Run scalafmt on VerilogEmitter

This PR adds options for memory initialization inside or outside the
`ifndef SYNTHESIS` block.

* Fix Mill support for non-M1 Macs

* Update build.sc

Co-authored-by: edwardcwang <edwardcwang@users.noreply.github.com>

Co-authored-by: edwardcwang <edwardcwang@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

CSESubAccesses was intended to be a simple workaround for a quadratic
performance bug in RemoveAccesses but ended up having tricky corner
cases and was hard to get right. The solution to the RemoveAccesses
bug--quadratic expansion of dynamic indexes of vecs of aggreate
type--turned out to be quite simple and makes CSESubAccesses much less
useful and not worth fixing.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* add --no-constant-propagation to disable constant propagation

* add test

* deprecate DisableFold.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Fix bug in zero-width memory removal

Correctly remove all extraneous connections to all types of memory
ports (read, write, readwrite) for zero-width memories.  Previously,
only read ports were correctly handled.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* fixup! Fix bug in zero-width memory removal

* fix for #2071
* add mill compile to CI

This fixes an error with negating a negative SInt literal and a
[debatable] lint warning in Verilator when negating any value.

This behavior matches that of Chisel (which directly emits the 0 - x
already).

Previously, InlineCasts could inline complex (ie. non-cast) Expressions
into other complex Expressions. Now it will only inline so long as there
no more than 1 complex Expression in the current nested Expression.

Co-authored-by: Albert Magyar <albert.magyar@gmail.com>

Due to inlining of Boolean expressions, the following circuit is handled
directly by the VerilogEmitter:

input a: UInt<4>
input b: SInt<1>
output o: UInt<5>
o <= dshl(a, asUInt(cvt(b)))

Priot to this change, this could crash due to mishandling of cvt in the
logic to inject parentheses based on Verilog precedence rules.

This is a corner case, but similar bugs would drop up if we open up the
VerilogEmitter to more expression inlining.

Previously, concatenating two SInts where one is of zero-width would
return the non-zero-width SInt. This is incorrect because the output of
Cat should be of type UInt. Now the ZeroWidth transform will introduce a
cast when removing a Cat when the argument type is non-UInt.

The flow of a LHS SubAccess node may still be SourceFlow if the type of
the Vec element has a flip. Tweak the logic of CSESubAccesses to check
every Expression flow while recursing instead of just the flow of the
final SubAccess.

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This PR adds a new annotation allowing inline loading for memory files
in Verilog code.