Before, the verilog emitter would connect registers to the invalid ports
and use random initialization on the generated registers.

It is better to generate wires instead and use random assignment on the
wires.

We previously had `ifdef guards on some parts of the emitted verilog to
control whether some registers or nets should be given random initial
values. These guards were all dependent on the RANDOMIZE macro.

However, there were actually three separate cases being controlled

 1. Giving random values to disconnected wires
 2. Random initialization of registers
 3. Random initialization of memories

It is possible that the designer would want to switch these three on or
off independently in simulation. For instance, the latter two are
usually safe because registers and memories will get some definite
binary value at power on in the actual circuit, but the first one can
be quite dangerous because the undriven wire could be metastable.

This change provides separate macros for each of the three sets of
guards so that they can be controlled independently.

* Updated FIRRTL spec + related code for readwrite ports.
    (write) data -> wdata & mask -> wmask for clarity

* Also removed simple.fir that snuck into master branch.

Now prints usage when given incorrect arguments

Also added clock to reg's abstract syntax

Added help string #234

* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)

Add missing case for connecting ClockType

fix read port enables in RemoveCHIRRTL
LGTM -chick

read port enables for cmems should always be high

Don't create output files until the compiler succeeds

Creating the output file preemptively screws up make, as on
subsequent executions of make, it thinks the task succeeded.

Bugfix: recursing stmts to remove unknown widths

* Added RemoveEmpty.scala, which removes Empty and nested Blocks

* Reused squashEmpty from ExpandWhens by moving it to Utils

* Squash EmptyStmts in ExpandWhens correctly

Change serialize to abstract method on FirrtlNode

Fix mem infer

turned on with '--inferRW <circuit name>'

Fix use of global state in instance loop checking

Change default log level to warn

Refactor RemoveAccesses and fix bug #210.

Also increase sensitivity of thread safety checking
Fixes #159

remove ConstProp in HighFirrtlToMiddleFirrtl

Fix StringSpec generators to only choose from valid values.