Signed-off-by: Jean Bruant <jean.bruant@ovhcloud.com>
(cherry picked from commit 6e0e7605

)

Co-authored-by: John's Brew <46595442+johnsbrew@users.noreply.github.com>

* Add SubAccess case to Utils.splitRef

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Update Utils.splitRef to use IR types

Change Utils.splitRef to use the actual IR types instead of their
WIR aliases. Update the Scaladoc note to reflect this.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 81ff0fe3

)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Deprecate firrtl.passes.ToWorkingIR

Deprecate ToWorkingIR as it is now an identity transform.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Deprecate firrtl.stage.Forms.WorkingIR

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Switch from Forms.WorkingIR to Forms.MinimalHighForm

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit fd5d4422

)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This allows ConstantPropagation to be used in cases where
ValidIfs need to be maintained, e.g., in the formal backend.

Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit ad0fd657

)

Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>

Fixes bug with mul or div followed by cat.
Also fixes some Verilog lint issues.

(cherry picked from commit 651fbe93

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Check Unidoc on all versions of Scala

  It is required for publishing and we publish every version

* Fix conflicting cross-version suffixes issue

  When running `sbt ++2.13.4 unidoc`, SBT would set the Scala version
  for the fuzzer and benchmark projects even though they aren't really
  relevant to the command. This may be a misconfiguration or a bug in
  the unidoc plugin. Whatever the case, simply making it possible for
  them to use the same version of Scala as the firrtl project (on which
  they depend) fixes the issue.

* Match versions of Scala in build.sbt and CI

* Fix unidoc issues in 2.13.4

  There is some bug in ScalaDoc not finding some links in firrtl.options
  so those links were made absolute as a workaround.

(cherry picked from commit aec9e9e6)

* Bump to Scala 2.12.13 and 2.13.4 (#2053)

(cherry picked from commit e3230941

)

# Conflicts:
#	build.sbt

* Resolve backport conflicts

Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit 031fe138

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

This adds a --dont-fold options (backed by a DisableFold annotation)
that lets a user specify primitive operations which should never be
folded. This feature lets a user disable certain folds which may be
allowable in FIRRTL (or by any sane synthesis tool), but due to inane
Verilog language design causes formal equivalence tools to fail due to
the fold.

Add a test that a user can disable `a / a -> 1` with a
DisableFold(PrimOps.Div) annotation.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit 698a9dca

)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Fix scalafmtCheckAll failures that snuck through
(cherry picked from commit 6d8e9041)

(cherry picked from commit 28829123

)

Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>
Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit bbd7fc41)

* Fix .run_formal_checks for Github Actions instead of Travis
* Remove .run_chisel_tests

Because we publish SNAPSHOTs on every merge to master, the Chisel repo
checks against master of FIRRTL regularly

* Only run unidoc for Scala 2.12

Under Travis we ran for 2.11, 2.12, and 2.13, but it doesn't work when
using ++2.<major>.<minor> when major != to 2.12. It seems if we want to
run all 3, we have to run as `sbt +unidoc`. It's not clear how much
benefit we get from building on the other versions, so stick with 2.12
for now.

* Generate .mergify.yml with script in chisel-repo-tools

Generated with config:

conditions:
  - status-success=all tests passed
branches:
  - 1.2.x
  - 1.3.x
  - 1.4.x

* Improve performance of LowerTypes renaming (#2024)

This is done by having LowerTypes uses two RenameMaps instead of one for
each module. There is one for renaming instance paths, and one for
renaming everything within modules.

Also add some utilities:
* TargetUtils for dealing with InstanceTargets
* RenameMap.fromInstanceRenames

(cherry picked from commit 15013df6

)

* Add MiMa waiver

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 93869cce

)

Co-authored-by: Megan Wachs <megan@sifive.com>

(cherry picked from commit 5fb8845f

)

Co-authored-by: XinJun Ma <xinjun.ma@qq.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit b02bea66

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

This is now set by sbt-ci-release

(cherry picked from commit 862aaec4

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

sbt-ci-release changes the commands required to publish to Sonatype.
While this may be a desirable change at some point, it is inconsistent
with other repos. Reverting for the time being.

(cherry picked from commit 594f783b

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* add test for RemoveAccessesSpec.

* fix nested SubAccess bug.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit 6c5ce834

)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

* Add SortModules to transform to def-before-use

Adds a new transform, SortModules, that transforms a FIRRTL circuit
to enforce an invariant of modules and external modules being defined
before use. This transform is left as optional in the event that a
user may wish to have a quick way of getting the circuit to respect
this property as may be expected of some other tool, e.g., MLIR.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Add test of SortModules transform

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit 4e46f8c6

)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Verilator 4.034 was complaining about wires being named weak and strong
because those are SV 2009 keywords.  Added them to the Utils.v_keywords list

(cherry picked from commit 3be73de2

)

Co-authored-by: Tim Snyder <timothy.snyder@sifive.com>

* Make MultiTargetAnnotation.targets a def

This enables the annotation writer to choose their own underlying data structure

* Update MultiTargetAnnotation ScalaDoc

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit cd845bdb

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Seq[(Int, DoPrimGen)] to Map[ExprGen[_ <: Expression], Int]

(cherry picked from commit d645921b

)

Co-authored-by: JADE KIM <60634081+jadekim727@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit b249814d

)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

(cherry picked from commit c9feb47d

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* smt: add support for write-first memories (#1948)


(cherry picked from commit 7d637e25

)

* smt: add old functions for binary compatibility

Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Automatically publish SNAPSHOTs on pushes to master (#1955)

Uses sbt-ci-release for automation

(cherry picked from commit 06843bd9

)

# Conflicts:
#	.travis.yml
#	project/plugins.sbt

* Fix merge conflicts

Co-authored-by: Jack Koenig <koenig@sifive.com>

It would replace them with a validif node with a UIntLiteral which can
lead to type errors.

(cherry picked from commit c7bbb75b

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* smt: add test for write port collision

* smt: add missing call to insertDummyAssignsForMemoryOutputs

* smt: fix typo in write port code

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* smt: add tests for assert name clashes

* smt: ensure unique signal names with a namespace

this fixes issues #1934

(cherry picked from commit fe95544d

)

Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>

* split big Emitter to submodules.

* fix all deprecated warning.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit 92af63c5

)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

(cherry picked from commit 1d0b1138

)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

(cherry picked from commit 8d765c98

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Add MiMa binary compatibility checking

One more bugfix for 1.4.0

Fix "fix" for negative literals > 32 bits

Overflow of 32-bit Int would cause any negative literal value equal to
-(2^(width % 32 - 1)) where width >= 32 to be incorrectly inverted

Merge master to 1.4.x for 1.4.0

VerilogMemDelays: fix lowering of direct mem-to-mem connections