- Dec 30, 2020
- Dec 12, 2020
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mergify[bot] authored
(cherry picked from commit 93869cce ) Co-authored-by:
Megan Wachs <megan@sifive.com>
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- Dec 08, 2020
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mergify[bot] authored
Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit b02bea66 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Dec 05, 2020
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mergify[bot] authored
This is now set by sbt-ci-release (cherry picked from commit 862aaec4 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Dec 03, 2020
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mergify[bot] authored
sbt-ci-release changes the commands required to publish to Sonatype. While this may be a desirable change at some point, it is inconsistent with other repos. Reverting for the time being. (cherry picked from commit 594f783b ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Nov 24, 2020
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mergify[bot] authored
* Make MultiTargetAnnotation.targets a def (#1969) * Make MultiTargetAnnotation.targets a def This enables the annotation writer to choose their own underlying data structure * Update MultiTargetAnnotation ScalaDoc Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit cd845bdb ) # Conflicts: # src/main/scala/firrtl/annotations/Annotation.scala * Resolve merge conflicts Co-authored-by:
Jack Koenig <koenig@sifive.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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mergify[bot] authored
Verilator 4.034 was complaining about wires being named weak and strong because those are SV 2009 keywords. Added them to the Utils.v_keywords list (cherry picked from commit 3be73de2 ) Co-authored-by:
Tim Snyder <timothy.snyder@sifive.com>
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- Nov 17, 2020
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mergify[bot] authored
(cherry picked from commit c9feb47d ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Nov 14, 2020
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mergify[bot] authored
* Automatically publish SNAPSHOTs on pushes to master (#1955) Uses sbt-ci-release for automation (cherry picked from commit 06843bd9 ) # Conflicts: # .travis.yml # project/plugins.sbt * Resolve merge conflicts Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Nov 10, 2020
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mergify[bot] authored
* -full64 is required to detect VCS. (#1930) (cherry picked from commit 1d0b1138 ) # Conflicts: # src/main/scala/firrtl/FileUtils.scala * Update FileUtils.scala Co-authored-by:
Jiuyang Liu <liu@jiuyang.me> Co-authored-by:
Adam Izraelevitz <azidar@gmail.com>
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- Oct 14, 2020
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mergify[bot] authored
* Faster dedup instance graph (#1732) * dedup: add faster InstanceGraph implementation and use it in dedup The new implementation takes care not to hash the instance types contained in DefInstance nodes. This should make dedup considerably faster. * FastInstanceGraph: cache vertices for faster findInstancesInHierarchy * FastInstanceGraph: remove the parent name field since it isn't actually necessary * FastInstanceGraph -> InstanceKeyGraph * InstanceGraph: describe performance problems. * InstanceKeyGraph: turn moduleMap into a def instead of a val This will make changing implementation details much easier in the future. * InstanceKeyGraph: return childInstances as Seq instead of Map This ensures a deterministic iteration order and it can easily be turned into a Map for O(1) accesses. * InstanceKeyGraph: add tests for public methods * InstanceKeyGraph: group public methods together * InstanceKeyGraphSpec: fix wording of a comment Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 1b9f4ddf ) # Conflicts: # src/main/scala/firrtl/transforms/Dedup.scala * Fix conflicts Co-authored-by:
Kevin Laeufer <kevin.laeufer@sifive.com> Co-authored-by:
Jack Koenig <koenig@sifive.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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mergify[bot] authored
* Better error messages for unserializable annotations (#1885) (cherry picked from commit 47c81ee3 ) # Conflicts: # src/main/scala/firrtl/annotations/AnnotationUtils.scala # src/test/scala/firrtlTests/annotationTests/JsonProtocolSpec.scala * Fix conflicts Co-authored-by:
Jack Koenig <koenig@sifive.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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mergify[bot] authored
Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 7174098c ) Co-authored-by:
Jiuyang Liu <liujiuyang1994@gmail.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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mergify[bot] authored
Force a synchronization point on InferWidths.run due to get a lock on the mutable constraint solver. This prevents a rare threading issue where the same compiler is run multiple times in parallel. This is a backport of #1775 using a different technique that is binary compatible with the 1.3.x. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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- Oct 13, 2020
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Adam Izraelevitz authored
Bump MiMa previous artifacts to 1.3.2
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- Oct 09, 2020
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Jack Koenig authored
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- Oct 01, 2020
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mergify[bot] authored
* Backport #1908 Co-authored-by:Albert Magyar <albert.magyar@gmail.com>
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- Sep 15, 2020
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mergify[bot] authored
Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 5f410f0e ) Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- Sep 11, 2020
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mergify[bot] authored
Co-authored-by:
chick <chick@qrhino.com> Co-authored-by:
Albert Magyar <albert.magyar@gmail.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit a8295871 ) Co-authored-by:
Kevin Laeufer <kevin.laeufer@sifive.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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mergify[bot] authored
* Add test for mem port clock legalization Co-authored-by:Albert Magyar <albert.magyar@gmail.com>
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mergify[bot] authored
* Async reset tieoff bug (#1854) * Elide emission of literals for async reset in sensitivity lists * Deprecate LegalizeClocksTransform Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 72d3983b ) # Conflicts: # src/main/scala/firrtl/transforms/LegalizeClocksAndAsyncResets.scala # src/test/scala/firrtlTests/AsyncResetSpec.scala # src/test/scala/firrtlTests/transforms/LegalizeClocks.scala * Resolve merge conflicts for BP PR#1861 Co-authored-by:
David Biancolin <biancolin@eecs.berkeley.edu> Co-authored-by:
David Biancolin <david.biancolin@gmail.com>
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mergify[bot] authored
(cherry picked from commit e87f3f63 ) Co-authored-by:
Albert Magyar <albert.magyar@gmail.com>
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- Aug 07, 2020
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mergify[bot] authored
Adds missing deprecation warnings to firrtl.Compiler methods: compile and compileAndEmit. This provides a more informative message to the user about how to actually migrate. Without this, the user only has the generic deprecation warning about class Compiler. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit e44cb05e ) Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- Aug 01, 2020
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mergify[bot] authored
* add sign-extend const-prop test * Emitter: don't wrap Neg operand in concat (cherry picked from commit b24b9a01 ) Co-authored-by:
Albert Chen <40366337+albertchen-sifive@users.noreply.github.com>
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Albert Chen authored
* add const prop bitwise reduction equivalence test * mask negative literals when propagating reduction * change widths * get rid of unnecessary if * add BigInt mask utility
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- Jul 31, 2020
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mergify[bot] authored
* test const prop of addition of negative literals * Emitter: handle minimum negative values correctly * update expected verilog in AsyncResetSpec (cherry picked from commit ea558ad7 ) Co-authored-by:
Albert Chen <40366337+albertchen-sifive@users.noreply.github.com>
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mergify[bot] authored
* ConstProp: test bitwise op of signed literals * ConstProp: use bit mask for FoldOr/FoldXor * handle and also * add UIntLiteral.masked helper Co-authored-by:
Jack Koenig <koenig@sifive.com> (cherry picked from commit 1927dc65 ) Co-authored-by:
Albert Chen <40366337+albertchen-sifive@users.noreply.github.com>
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- Jul 30, 2020
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mergify[bot] authored
* WiringUtils.sinksToSources: make sinkInsts order deterministic * WiringUtils: make owners a LinkedHashMap * Wiring: only make something a Wire if it isn't a port already Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit c02c9b7f ) Co-authored-by:
Kevin Laeufer <kevin.laeufer@sifive.com>
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- Jul 21, 2020
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Albert Chen authored
* add test to check that RemoveIntervals fixes kinds * RemoveIntervals: run ResolveKinds Co-authored-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- Jul 18, 2020
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mergify[bot] authored
Add cross-building of unidoc to test issues if a user later does a +publishLocal (like with Chisel CI). Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> (cherry picked from commit 5f70175d ) Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- Jul 17, 2020
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Schuyler Eldridge authored
Remove overlapping inputForm=LowForm tests (bp #1753)
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Schuyler Eldridge authored
Refactor the test used in the CustomTransformSpec to assert that inputForm=LowForm legacy transforms run right before the emitter (see note below!). The new test looks only for a list of (customTransform, emitter) in a sliding, size-2 window of the flattened transform order. Previously, this was looking for a match before and after the custom transform. The old implementation necessitate busywork updates of the test when new transforms are added that changed the transform running before the custom transform. Note: this test, as written is intentionally wrong. When the LegalizeAndReductionsTransform was added, this was placed after inputForm=LowForm and before the Verilog emitters. However, the test is supposed to ensure that an inputForm=LowForm transform runs immediately before its emitter. I'm intentionally leaving the test broken. This behavior can be changed in a follow-on commit if need be. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> (cherry picked from commit debee429)
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Schuyler Eldridge authored
Remove tests from LoweringCompilerSpec testing the placement of inputForm=LowForm legacy, custom transforms. This behavior is already tested in the CustomTransformSpec. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> (cherry picked from commit f5dd8ddc) # Conflicts: # src/test/scala/firrtlTests/LoweringCompilersSpec.scala
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- Jul 15, 2020
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mergify[bot] authored
Add an optionalPrerequisiteOf to TopWiringTransform pointing at LowerTypes. This fixes a bug where top-wired wire bundles with flips could result in the top-wired, flattened bundle having every field with an "output" direction if the TopWiringTransform is moved around in the transform order (see FIRRTL issue #1744). Why did this happen? Fundamentally, this stems from the fact that LowerTypes preserves bundle direction for ports, but destroys it for wires. Specifically, The TopWiringTransform creates ports of the "output" direction that are copies of the underlying type of the component being top-wired. Before LowerTypes, the type of a bundle has direction information via flips. After LowerTypes, the lowered ground type does not have this information. Therefore, all the ports are ground type outputs. Simply ensuring that TopWiringTransform must run before LowerTypes avoids this problem. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 005a3d16 ) Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- Jul 14, 2020
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mergify[bot] authored
Changed from target/<scala-version>/src_managed/main/firrtl/ to target/<scala-version>/src_managed/main/compiled_protobuf/firrtl/ The protobuf generation clears its target directory so it would clear the generated ANTLR-generated files. (cherry picked from commit c14330d6 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Jun 26, 2020
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mergify[bot] authored
* Batch renames in LowerTypes Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> * Add benchmarking for LowerTypes Add infrastructure of benchmarking Transforms (in addition to existing infra for Passes). Also run System.gc between each timed benchmark to improve stability. Co-authored-by:
Jack Koenig <koenig@sifive.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 87c5d034 ) Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com>
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chick authored
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chick authored
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- Jun 25, 2020
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mergify[bot] authored
* Build ArrayBuffers in Block.mapStmt (#1669) * Build ArrayBuffers in Block.mapStmt * Have empty Block serialize as "skip" The FIRRTL parser requires at least one indented line in each module. Sometimes tests emit and parse modules with no contents; this ensures there's always at least a "skip" in empty modules. Also fix tests that expected certain skips * Use var List as stack in Block.mapStmt impl This replaces Iterator concatenation. In Scala 2.11, RHS recursion on Iterators is not stack safe. This seems to have been fixed in 2.12 by Scala PR 5033. Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 1e497ce3 ) # Conflicts: # src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala # src/test/scala/firrtlTests/annotationTests/MorphismSpec.scala * Fixup for 1.3.x Co-authored-by:
Jack Koenig <koenig@sifive.com>
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