Verilog emitter transform InlineNots (bp #1270) (#1295)

* Verilog emitter transform InlineNots (#1270)

[skip formal checks]

* ConstProp FoldEqual/FoldNotEqual propagate boolean (non-)equality with true/false
* transform InlineNots
* transform back-to-back Nots into straight rename
* swap mux with inverted select

Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
(cherry picked from commit f77487d3

)

* Fix .run_formal_checks.sh skipping logic

Fetch and checkout the base branch before attemping to inspect the log

Co-authored-by: John Ingalls <43973001+johningalls-sifive@users.noreply.github.com>
Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>