Unverified Commit 90a04e89 authored by mergify[bot]'s avatar mergify[bot] Committed by GitHub
Browse files

Create annotation to allow inline readmem in Verilog (#2107) (#2108)

This PR adds a new annotation allowing inline loading for memory files
in Verilog code.

(cherry picked from commit efdefde2

)

Co-authored-by: default avatarCarlos Eduardo <carlosedp@gmail.com>
parent a0bc0673
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment