Cleanup verilog emitter casts (bp #1264) (#1299)

* Remove unnecessary casts in Constant Propagation

(cherry picked from commit df48d61c)

* Remove unnecessary $signed casts for PrimOps in Verilog Emitter

[skip formal checks]

Adds new InlineCastsTransform to the VerilogEmitter which removes
Statements that do nothing but cast by inlining the cast Expression

(cherry picked from commit c16ef85c)

* Fix literals cast to Clocks in Print and Stop

Many tools don't except 'always @(posedge 1'h0)' so we assign the
literal to a wire and use that as the posedge target.

(cherry picked from commit e27bb38c

)

Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>