Require Andr, Orr, Xorr, Neg to have one operand (#2312) (#2314)

Fix an OG bug where Andr, Orr, and Xorr would accept an arbitrary number
of operands.  Verilog emission doesn't support this and will silently
drop all operands after the first.  E.g., "andr(a, b)" would emit as
"&a".  After this commit, "andr(a, b)" will be rejected by checking
passes.

For archaeological purposes, this appears to have been the behavior
dating back to when this was added in d2d3260a

.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit a643cfd3

)

# Conflicts:
#	src/main/scala/firrtl/passes/CheckHighForm.scala

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>