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freechipsproject
firrtl
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split-pad-widths
b2156a77
·
DO NOT MERGE - Quick and dirty splitting of PadWidths
·
Dec 02, 2016
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rework-verilog-mem-delay
7e33cd79
·
WIP: partial reworking of verilog mem delay
·
Dec 08, 2016
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rewrite-emitter
f3ed1bb2
·
Fix exponential timing bug
·
Dec 12, 2016
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one-line-reg
8cb5a1cd
·
Emit DefRegister in a single-line
·
Jan 05, 2017
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node-count
ac62e3bf
·
Add node count utility. Note, this is very slow.
·
Feb 19, 2017
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ranged-widths
fd52788b
·
WIP: Interval types
·
Feb 22, 2017
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mas
1f9fd2f9
·
move more general utils out of memutils, mov WIR helpers to WIR.scala and update uses
·
Feb 23, 2017
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tutorial4
85fb4d64
·
Removed comments for picture
·
Mar 13, 2017
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improve-dce
f54f28d7
·
Bugfix the bugfix - now correctly dce reg
·
Mar 22, 2017
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fix-498
6ddd66ae
·
Fixed tests
·
Mar 22, 2017
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gate-count
faf93c6c
·
Added op counter xform
·
Mar 31, 2017
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list-invalid
370ab979
·
WIP: listing invalid wires for chris
·
Mar 31, 2017
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aggressive-dce
c580d660
·
WIP: Aggressive DCE
·
Apr 03, 2017
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fix-replmem-output-form
34e56eae
·
Make sure ReplaceMemTransform sets its outputform
·
Apr 05, 2017
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analog-rename-experiment
1d101f66
·
commit of experimental pass that changes the emission of analog types, based...
·
Apr 06, 2017
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identifier
c04e23f2
·
WIP adding Id, tons of compile errors
·
Apr 15, 2017
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improve-opt
1762201a
·
Actually remove Prints and Stops
·
Apr 24, 2017
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memoize-uinttype
be21a763
·
Memoize UIntType
·
Apr 28, 2017
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reorg
3c7d9947
·
Added mappers back to utils
·
May 22, 2017
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better-rand
e3277aa5
·
Refactor randomization
·
May 25, 2017
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