But is this true: `defaulting any unconnected fields to 0 (regardless of type)`
for either Bundles or Vec literals.

convert from mutable.LinkedHashMap to immutable.ListMap after generation to preserve key ordering

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

One test that broke is fixed

# Conflicts:
#	core/src/main/scala/chisel3/Aggregate.scala
#	src/test/scala/chiselTests/ChiselSpec.scala

Remove println and add some scaladoc

Making progress
Lits can now be specified and pack
Tests are being built

- restored some BundleLit tests
- working through a list of vec literal tests

- adds a cloneWithWidth method to LitArg subclasses

- Fixed problem with nested vec lits

Vec literals tests pass

A bit of cleanup

Made bundle-literals support vec literals underneath

Not a Pokémon

* Handle MemTypeBinding in Analog

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Fix stack trace trimming across ChiselStage

Fix bug in stack trace trimming behavior. Now, the following is what
happens:

1. The Builder, if catching accumulated errors, will now throw a
   ChiselException with a Scala-trimmed Stack trace. Previously, this
   would throw the full excpetion.
2. The Elaborate phase handles stack trace trimming. By default, any
   Throwable thrown during elaboration will have its stack
   trace *mutably* trimmed and is rethrown. A logger.error is printed
   stating that there was an error during elaboration and how the user
   can turn on the full stack trace. If the --full-stacktrace option
   is on, then the Throwable is not caught and only the first
   logger.error (saying that elaboration failed) will be printed.
3. ChiselStage (the class), ChiselStage$ (the object), and ChiselMain
   all inherit the behavior of (2).

Mutable stack trace trimming behavior is moved into an implicit
class (previously this was defined on ChiselException only) so this
can be applied to any Throwable.

No StageErrors are now thrown anymore. However, StageErrors may still
be caught by ChiselMain (since it is a StageMain).

Testing is added for ChiselMain, ChiselStage, and ChiselStage$ to test
all this behavior.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Make Data GC-able

No longer create a pointer from parent to every HasId, only do it by
default for BaseModules and MemBases. Add pointer from parent to Data
upon binding the Data.

* Add MemTypeBinding for port types of Mems

This binding is similar to the SampleElementBinding for Vecs in that
these Data are not truly hardware, but are represented in the FIRRTL IR
and thus need some representation.

* Call _onModuleClose on unbound Records

This maintains some corner-case behavior that is nevertheless relied
upon. It ensures that refs are set for the elements of Records, even if
they are not bound to any real hardware.

This is a new SBT build unit that symlinks in some files from the normal
chisel project tests, but builds them without the compiler plugin.

* Added SyncReadMem-based implementation of the Queue class

* Rework of the parametrized Queue class SyncReadMem-based implementation

* Modification of the parametrized Queue class SyncReadMem-based implementation

* Limiting the visibility of the read address for SyncReadMem-based Queue

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Signed-off-by: Jean Bruant <jean.bruant@ovhcloud.com>

* Fix some botched formatting (replace ```mdoc scala with ```scala mdoc)
* Replace some unnecessary uses of triple backticks with single
  backticks
* Move appendix docs from wiki-deprecated/ to appendix/
  * This will require an update on the website as well
* Update Bundle literal docs

* Update reported width from div/rem to match FIRRTL results

* Add tests for width of % and / on UInt and SInt

* Add loop-based test for known UInt/SInt op result widths

Co-authored-by: Jack Koenig <koenig@sifive.com>

If a method passed to higher function does not return any value,
it is prefer to use `foreach` instead of `map`.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

This is a nit fix. no logic is changed.

* Rename `typeName` to `enumTypeName` in ScalaDoc
* Add return type at public method
* Rename `enum_records` into `enumRecords` to retain name consistency

Co-authored-by: Jack Koenig <koenig@sifive.com>

Remove "val io" and rename MultiIOModule to Module

Co-authored-by: Megan Wachs <megan@sifive.com>

Chisel projects no longer need -Xsource:2.11 when compiling with Scala
2.12.

Autowrapping of "val io" for compatibility mode Modules is now
implemented using reflection instead of calling the virtual method.

Also move Chisel.BlackBox to new chisel3.internal.LegacyBlackBox

This PR revert #1480, but keep the test.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>