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  1. Oct 30, 2020
  3. Oct 28, 2020
  5. Oct 27, 2020
  7. Oct 23, 2020
    • Jack Koenig's avatar
      Use Data refs for name prefixing with aggregate elements (#1616) · 0745dede
      Jack Koenig authored 
      * Use Data refs for name prefixing with aggregate elements

Vecs set the refs of their elements upon construction of those elements.
In the past, Records haven't set their elements refs until module close,
but it can be done sooner. Doing it upon binding means that refs will at
least be available for Records used in hardware elements. Since only
bound Data can be connected to anyway, Aggregate elements being
connected to will always have a ref which we can then use for creating
naming prefixes.

* Add tighter correctness checks

* Handle more cases in connection prefixing

Add support for forcing setRef to override a previous setting. This
is only used by BlackBox ports which need to drop their io prefix.

Also add a Try() around Data.bindingToString which sometimes throws
exceptions when being used to .toString a Data in an error message.

* Strip trailing spaces in names in compiler plugin
      0745dede
  9. Oct 22, 2020
  11. Oct 20, 2020
  13. Oct 15, 2020
  15. Oct 14, 2020
    • Chick Markley's avatar
      ExtModule's lacked support built in support for providing (#1154) · fd92809e
      Chick Markley authored 
      * ExtModule's lacked support built in support for providing
the verilog source. This changes creates traits that
can be used with ExtModule to provide the support currently found in
BlackBox

- Add support for ExtModule helpers
  - HasExtModuleResource to use addResource
  - HasExtModuleInline to use setInline
  - HasExtModulePath to use addPath
- Add tests of the above support.
  - Note: These tests use Stage instead of Driver
- Added ScalaDoc for HasBlackBoxInline#setInline

* Fix the danged trailing commas.

* Change to use `.transform` as the correct API for `ChiselStage`
      fd92809e
  17. Oct 13, 2020
  19. Oct 12, 2020
  21. Oct 06, 2020
  23. Oct 02, 2020
    • Chick Markley's avatar
      Move Chisel3 to SPDX license conventions (#1604) · aa2c6224
      Chick Markley authored 
      Change source and other relevant files to use SPDX license
LICENSE file moved from src/ to ./
Changed license file to refer to this per recommendation
using_spdx_license_list_short_identifiers

WARNING: Tests fail with as of yet undiagnosed error
```
[error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15
[error] Failed tests:
[error] 	chiselTests.QueueSpec
[error] 	examples.VendingMachineGeneratorSpec
[error] 	chiselTests.HarnessSpec
[error] 	chiselTests.ConnectSpec
[error] 	chiselTests.aop.SelectSpec
[error] 	chiselTests.PopCountSpec
[error] 	chiselTests.CloneModuleSpec
[error] (Test / test) sbt.TestsFailedException: Tests unsuccessful
[error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM
sbt:chisel3>
```
      aa2c6224
  25. Sep 25, 2020
  27. Sep 22, 2020
  29. Sep 16, 2020
  31. Sep 15, 2020
  33. Sep 10, 2020
  35. Sep 05, 2020
    • Jack Koenig's avatar
      Better Building of FIRRTL From Source (#1563) · 05ac57c1
      Jack Koenig authored 
      Using JVM system properties sbt.sourcemode and sbt.workspace, one can now
easily build chisel3 with firrtl from source

Example use:

Assuming firrtl is cloned into the chisel3 root directory:
$ sbt -Dsbt.sourcemode=true -Dsbt.workspace=$PWD

Alternatively, one can set these properties in .sbtopts which can then
be committed, enabling building from source by default
      05ac57c1
  37. Sep 03, 2020
  39. Aug 28, 2020
  41. Aug 27, 2020
    • Schuyler Eldridge's avatar
      Add ChiselPhase, Stop writing files in ChiselStage$ methods, Expand ChiselStage$ helpers (#1566) · b0389cc9
      Schuyler Eldridge authored 
      

* Add ChiselPhase

* Use ChiselPhase in ChiselStage, remove targets

Switch from a one-off PhaseManager inside ChiselStage to actually
using the newly added ChiselPhase. This removes the targets
method (and API) from ChiselStage.

* Stop writing to files in ChiselStage$ methods

Change the ChiselStage companion object methods, elaborate and
convert, to not write files. Under the hood, these are switched from
using ChiselStage (which, like all phases, will write files) to using
ChiselPhase.

* Test that ChiselStage$ methods write no files

Modify existing ChiselStage object method tests to check that no files
are written.

* Expand ChiselStage$ API with more helpers

This adds additional methods to the ChiselStage object for going
directly from a Chisel module to a string including: CHIRRTL, high
FIRRTL IR, Verilog, and SystemVerilog.

Differing from their ChiselStage class counterparts, these take no
arguments other than the module and write no files.

* Add tests of new ChiselStage$ helper methods

* Use ChiselStage object in tests

Signed-off-by: default avatarSchuyler Eldridge <schuyler.eldridge@ibm.com>
      b0389cc9
  43. Aug 26, 2020
  45. Aug 22, 2020
  47. Aug 21, 2020
  49. Aug 15, 2020
  51. Aug 14, 2020