Now that ucbbar/chisel3-tools has Verilator 4.006, use that for tests.

Compatibility for rename introduced by #994

toString on Data subtypes will now print the type and optionally binding information including literals and IO names as feasible.

* Remove GhpagesPlugin. (#966)

* Restore old SCM reference (after removing ghpages)

- Fix BoringUtils deduplication bug, include new tests
- Update/clarify BoringUtils scaladoc

This compresses the Scaladoc for BoringUtils slightly by using 120
character lines and removing unnecessary whitespace.

This also changes the poorly named "dedup" parameter to the what it
actually is: "disableDedup".

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This adds two tests to the BoringUtilsSpec to explicitly verify that
deduplication is required when boring. This adds tests that both
verify that the test passes as expected with deduplication enabled and
that the same test fails with deduplication disabled.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This fixes a bug where BoringUtils non-hierarchical sinks would be
deduplicated even when specified that they should not be.

h/t @ucbjrl for discovering this!

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Unify internal (chisel3.core) and external (chisel3 / chisel3.experimental) Module class names (#994)

Fix scaladoc for UInt.unary_!

It performs the operation (x === 0.U), just like in C.   The scaladoc
incorrectly described it as performing the operation !x(0).  (Obviously, these
are equivalent for Bool, but not for UInt in general).

Generate better code for UInt.andR

In the case that the width is known, we can emit one fewer Firrtl node.

This obviously synthesizes the same way, but compiles/simulates faster.

Avoid procedural wire assignment in test resource

Verilator 4.008 dropped the hammer on procedural wire assignment to
align with the IEEE standard (first I've heard of this, though). The
VerilogVendingMachine.v test resource will error in Verilator 4.008
with a PROCASSWIRE error if you try to compile it. This fixes that
example to only assign to a register.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

JDK 11 `java.lang.String#lines` conflicts with Scala `StringOps#lines`.
This has been fixed in scalac 2.12.8 but projects using 2.11 in their
cross-build need the `Predef.augmentString` patch.

[Scala bug & fix reference](https://github.com/scala/bug/issues/11125)

**NOTE**: A `publishLocal` should replace the downloaded `.ivy2/cache/...` version with a pointer to the `.ivy2/local/...` version. To force refetching of the Sonatype repository version, you should delete both `.ivy2/{cache,local}/...` versions.

* Fix width propagation of non-literals in WireInit and RegInit
* Change .getWidth to throw an exception instead of calling .get
* Add utilities for checking inferred vs. known widths
* Add tests for Wire, WireInit, Reg, and RegInit width inference
* Add ScalaDoc for Reg, Wire, RegInit, and WireInit

Improve quality of code generation for UInt.-%

This is semantically equivalent, but gets rid of a bunch of Firrtl text.
It also gets rid of a bunch of Verilog, because Firrtl is capable of
pattern-matching the new expression into SubWrap.  The effect is that
we now get

    wire [4:0] in;
    wire [4:0] res;
    assign res = 5'h0 - in;

instead of

    wire [4:0] in;
    wire [5:0] _T_40;
    wire [5:0] _T_41;
    wire [4:0] res;
    assign _T_40 = 5'h0 - in;
    assign _T_41 = $unsigned(_T_40);
    assign res = _T_41[4:0];

asBools, asBool, and chained apply on asBools