Avoid procedural wire assignment in test resource

Verilator 4.008 dropped the hammer on procedural wire assignment to
align with the IEEE standard (first I've heard of this, though). The
VerilogVendingMachine.v test resource will error in Verilator 4.008
with a PROCASSWIRE error if you try to compile it. This fixes that
example to only assign to a register.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>