(cherry picked from commit e513da57)

# Conflicts:
#	build.sbt

(cherry picked from commit 68eb2486

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* [svsim] Make EphemeralSimulator multi-processing friendly (#3847)

(cherry picked from commit 1ff43c93

)

# Conflicts:
#	src/main/scala/chisel3/simulator/EphemeralSimulator.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 41dd2671

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 8f0196fa

)

Co-authored-by: Deborah Soung <debs@sifive.com>

* Report source locator in when scoping error messages (#3804)

(cherry picked from commit d21a6635

)

# Conflicts:
#	core/src/main/scala/chisel3/Data.scala

* resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Fix Reg() to properly handle clocks as rvalues (#3775)

Previously, it was not calling .ref. It was thus not properly:
1. Checking that the clock is bound hardware
2. Checking that the clock is visible in the current scope
3. Reifying the clock if its a view

Note that RegInit() was already correctly calling .ref.

(cherry picked from commit 1c348c55

)

# Conflicts:
#	src/test/scala/chiselTests/ClockSpec.scala

* Resolve backport conflicts

* fix test

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit b3b5ab19

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit d8991c55

)

Co-authored-by: Megan Wachs <megan@sifive.com>

* Bump versions
* It now tabs every line included in the Release Notes section of
  the PR template

(cherry picked from commit b00b22a1

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Update Scala CLI Template (#3757)

* Use "dep" instead of deprecated "lib"
* Add _root_ to `import circt.stage.ChiselStage`
  * Also add comment describing how this disambiguates from
    chisel3.util.circt when the user does `import chisel3.util._`
* Bump versions in Github workflows

(cherry picked from commit 589f1067

)

# Conflicts:
#	.github/workflows/build-scala-cli-template.yml
#	.github/workflows/build-scala-cli-template/chisel-template.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Support === on empty Aggregate (#3747)

(cherry picked from commit da6ae7dc

)

* Fix for Scala 2.12

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Fix using Definitions as arguments to Definitions (#3726)

(cherry picked from commit a050b8cd

)

# Conflicts:
#	core/src/main/scala/chisel3/Module.scala
#	core/src/main/scala/chisel3/experimental/hierarchy/core/Definition.scala
#	core/src/main/scala/chisel3/experimental/hierarchy/core/Instance.scala
#	core/src/main/scala/chisel3/internal/Builder.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: Aditya Naik <aditya.naik@sifive.com>
Co-authored-by: Tynan McAuley <tynan@niobiummicrosystems.com>
(cherry picked from commit 24de2f28

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Don't emit nodes when calling .asBool on a Bool

(cherry picked from commit d5e65a33

)

# Conflicts:
#	src/test/scala/chiselTests/LTLSpec.scala
#	src/test/scala/chiselTests/VerificationSpec.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: jackkoenig <koenig@sifive.com>

* Add --dump-fir option to ChiselStage (#3453)

This option will dump the .fir before invoking firtool.

Additional changes:
* Use os.lib for invoking firtool
* Use lazy serialization to avoid holding the entire FIRRTL in
  memory.
* Mix NoStackTrace into FirtoolNotFound
* Fix detection of no firtool

(cherry picked from commit 4db86b2f

)

# Conflicts:
#	src/main/scala/circt/stage/CIRCTOptions.scala
#	src/main/scala/circt/stage/ChiselStage.scala
#	src/main/scala/circt/stage/phases/CIRCT.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 3382cab2

)

Co-authored-by: Vladimir Milovanović <barun@eecs.berkeley.edu>

* Add support for configurable warnings (#3414)

Warnings have been assigned unique integers to use as identifiers for
purposes of documentation and configuration.

New CLI option --warn-conf accepts a comma-separated sequence of
<filter>:<action> pairs for customizing warnings.

Supported filters are:
* any          - matches all warnings
* id=<integer> - matches warnings with the integer id
* src=<glob>   - matches warnings where <glob> matches the warning
                 source file

id and src filters can be combined with &.

Supported actions are:
* :s - suppress the warning
* :w - report the warning as a warning (default behavior)
* :e - error on the warning

For example, the new Vec dynamic width matching warning can be
suppressed for source files in src/main/scala while all other warnings
elevated to errors with:
  --warn-conf "id=4&src=src/main/scala/**:s,any:e"

The is also --warn-conf-file which works similarly to --warn-conf except
the <filter>:<action> pairs are newline separated in a file. # is used
for line comments.

(cherry picked from commit 8e33a68b

)

# Conflicts:
#	core/src/main/scala/chisel3/Aggregate.scala
#	core/src/main/scala/chisel3/internal/package.scala
#	src/test/scala/chiselTests/ConstSpec.scala
#	src/test/scala/chiselTests/ProbeSpec.scala

* Resolve backport conflicts and binary compatibility issues

Also make code compile with Scala 2.12

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Upgrade mill to 0.11.0 (#3367)

Also add mill to CI.

(cherry picked from commit 1f485a1a

)

# Conflicts:
#	build.sc

* Resolve backport conflicts

---------

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

This fixes Scala compiler warnings in Scala 2.13.12 requiring type
ascriptions on public implicit definitions.

(cherry picked from commit d011b443

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* bug fix for decoderbundle not being able to be lhs op

* add default field for DecodeField for DecodeTable non X case

* add test to show DecodeField default use case

(cherry picked from commit 7466789a

)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

(cherry picked from commit e6c07b37

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 1ae807ac

)

Co-authored-by: Mads Rumle Nordstrøm <85681203+madsrumlenordstrom@users.noreply.github.com>

(cherry picked from commit 53a86258

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit b904c195

)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

(cherry picked from commit 6de7cce4

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Sanitize Record._elements (#3419)

This moves name sanitation a little earlier and ensures that the
sanitized names are use more consistently throughout Chisel internals.

This fixes a bug in D/I where unsanitary names would lead to a crash.

(cherry picked from commit 5c282db5

)

* Keep Scala 2.12 support by not using VectorMap

* Fix firrtl in tests for older firrtl spec version

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* SRAM API: Add multiple-clocked port API (#3383)

This PR adds new APIs for the SRAM module to instantiate a number of ports connected to individual clocks. This allows the creation of memories driven by multiple clocks, for use cases like clock domain crossover.

(cherry picked from commit d79ae71e

)

---------

Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
Co-authored-by: Jared Barocsi <jared.barocsi@sifive.com>

[svsim] Don't redirect simulation stderr to a pipe (#3403)

(cherry picked from commit e51fa08c

)

Co-authored-by: George Lyon <GeorgeLyon@users.noreply.github.com>

* Deprecate calling .viewAs on non-hardware (#3395)

It's an error in most cases already, and in the cases it isn't, make it
a warning. Also fix a crash that could occur when viewing a non-Data
containing non-hardware Data.

(cherry picked from commit 1e524de9

)

# Conflicts:
#	src/test/scala/chiselTests/experimental/DataView.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

This is not a functional bug. The recursive form of reify for Element
would use the .topBinding from the wrong argument, so it would recurse
an extra time, but it would ultimately converge to the right value.

(cherry picked from commit 374b45b9

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Support literals and DontCare in DataView targets (#3389)

(cherry picked from commit 0f803cd8

)

# Conflicts:
#	src/test/scala/chiselTests/experimental/DataView.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* log2 functions
* unsignedBitLength

(cherry picked from commit 88fecfc1

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 2e95804f

)

Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 8851faed

)

Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>

(cherry picked from commit b910bf94

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Allow IntrinsicModule to be used in Instantiate

Change a few `RawModule`s to `BaseModule`s to allow for intrinsic
modules to be used with the instantiation API.

* Add tests for Instantiate of non-RawModules

---------

Co-authored-by: Fabian Schuiki <fabian@schuiki.ch>
(cherry picked from commit 951f8b7c

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit e718aac1

)

Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

(cherry picked from commit c81c9f18

)

Co-authored-by: Megan Wachs <megan@sifive.com>