Adds additional Scaldoc to the RegNext object that (1) indicates that
the width is not set and (2) shows an example of how to construct a
RegNext-like construct with a set width.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit b171f20d

)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit f1c4395b

)

Co-authored-by: Leway Colin <colin4124@gmail.com>

* Remove redundancy code

* Remove blank line

* BitPat supports whitespace and underscores, presumably for human readability.
The BitPat.parse factory though did not remove these from the returned count.
This fixes that adds whitespace and underscores to the unit tests
This is an updated vesion of Chisel PR #1069

Co-authored-by: Chick Markley <chick@qrhino.com>
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit 160e019e

)

Co-authored-by: Leway Colin <colin4124@gmail.com>

(cherry picked from commit c7715c16

)

Co-authored-by: Deborah Soung <debs@sifive.com>

(cherry picked from commit 0a98a82c

)

Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>

This is just a band aid until an Aggregate `isLit()` method (for which work has begun) is implemented.

(cherry picked from commit 98a6710c)

This reverts commit 5a0f0666.

(cherry picked from commit 03bbb258)

(cherry picked from commit 8edca94f)

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit a301fa12)

Data.isLit called Data.litArg which would trigger a Chisel runtime
deprecation warning in user code with source locator Data.scala:488

(cherry picked from commit afef8b8c)

This switches from using an implicit val that required awkward
suppression (as illustrated in CompileOptionsSpec) to allowing
overriding in the same way as done in "import chisel3._" via the
creation of an implicit val in lexical scope.

(cherry picked from commit 2c53527f)

(cherry picked from commit d4f64fa6)

* Add brief description of (current) chisel versioning and version recommendations.

* Respond to comments.
Replace "semantic versioning" with "a form of semantic versioning".

* Respond to comments - replace mmddyy with yyyymmdd.

* Mention change in SNAPSHOT naming.

(cherry picked from commit 041fd377)

* Better anonymous and class-in-function desiredName

This changes the desired name of a Module to provide non-numeric
naming for anonymous Modules and Modules defined inside function
bodies.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit a69d79f2

)

* Tests for anonymous/class-in-module desiredName

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit 77d2455a)

Accomplished by changing the code gen for casting literals to
aggregates. Rather than connecting the literal to a wire that is then
bit selected from, just bit select from the literal which saves the
creation of an intermediate wire and matches FIRRTL's semantics for
legal async reset initial values.

(cherry picked from commit 92d88ffb)

* Add CCC20 Info at README top

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Add Upcoming Events h2 Heading to README.md

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit 185710d0)

Also specify 3.2.x/1.2.x branches for CircleCI

This reverts commit 7b93b0f8.

Make ChiselStage targets not private

This enables users to use the nice run method of `ChiselStage` with their own set of phases.

Internal BoringUtils.bore Bug Fix

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This fixes a bug where internal boring using BoringUtils.bore would
fail because it was using instanceName which cannot be called before
the module closes. Previously, this meant that BoringUtils.bore would
work for boring instances (which are closed in a parent), but not for
boring signals in the current, unclosed module.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Plan to be released with 3.3.

Breaks experimental Range API.
Adds new Interval type and associated support.

This commit adds the following:

- Renamed Range to IntervalRange to avoid name collision with scala Range
- Changed RangeTransform macro to Return an IntervalRange
  - Improved error messages on missing comma or decimal
  - Added notational support for binary point
  - Some formatting cleanup also
- SIntFactory
  - Change to use IntervalRange API
- UIntFactory
  - UInt from range has custom width computation
    - It does not need to deal with lowerbound extending bit requirements
    - Code to handle special case of range"[0,0]" to have a width of 1
- IR.scala
  - Removed Bound and other constraint code that was duplicating firrtl stuff
  - Added new RangeType
  - Added IntervalRange class and object
- RangeSpec
  - modified just a bit to handle notational differences
    - previous range interpolator returned tuple now returns IntervalRange
- Add IntervalType to emitter
- Added IntervalSpec with many tests
- Added ScalaIntervalSimulatorSpec which tests golden model for Interval
- Added ScalaIntervalSimulator which is a golden model for Interval
  - This gold may not have been polished to a high sheen
- Add IntervalLit cases to Converter
- Add Interval PrimOps to IR
  - asInterval, wrap, squz, clip, setp, decp, incp
  - Add IntervalLit class to IR
- Add Interval to MonoConnect
- Add Interval Type to Bits (in experimental package)
  - add conversions to Interval from other types
- Add Interval clone stuff to Data
- Add Literal creation helpers to chisel3 package
  - these may move to experimental if I can figure that out

Dynamically indexing a Vec of Flipped bidirectional Bundles would get
the wrong directions on the elements of the Bundles

Fixes #1192

Strip Object and Outer Class from desiredName