this does not test clean due to bug in firrtl

adjust tests accordingly

Used for stitching Verilog inout through Chisel Modules (from BlackBox
to BlackBox)

There was some dubious (certainly unclear) code organization in the CompatibiltySpec tests. The isPow2() test was randomly failing in Jenkins builds. This may address the problem.

* Fix up Absolute value #abs
Defines #abs in Num
Implement #abs in UInt
Change #abs in SInt to return an SInt
Change #abs in FixedPoint to return a FixedPoint
Added  a couple of tests
Add some scala style suppression to Bits so I can read code in IntelliJ

* Per review
Add tests that abs works for positive values
Added SInt and UInt tests for abs to new underpopulated IntegerMathSpec
Used fixed point literals in fixed points abs definition

Retain un-deprecated SeqMem in compatibility mode, deprecate in chisel3.

* Added vec IO tests for #104

* Added Vec test case for Reg of vecs

* Change Vec creation to check if gen is lit (and hence needs to be declared)
Fixes #104

* Fix tests (add IO())), Vec.fill()

* Fix deprecated usage.

* Add Binding IO() NPE fix so tests pass.

* Fix style - use space consistently.

* Fix style - use space consistently.

* Move to cookbook
* Change FSM implementation to use switch & is
* Add non-FSM implementation
* Add execution-driven test

* Move copyResourceToFile() to BackendCompilationUtilities.
* Move BackendCompilationUtilities into a firrtl util package.
Some of this could be moved into a more general tools package, but since chisel3 already has a dependency on firrtl ...
* Push util down into firrtl so as not to conflict with scala.util.
* Use new createTestDirectory. Fixes #452.

Fix default suggested name of Module instances (now based on desired name
rather than actual assigned name).
Remove parent/child relationship from Namespace.

Previously, Module and Bundle namespaces were "children" of the Module
definition namespace. This could lead to collisions that would give unexpected
names for module instances or Bundle elements. In particular, otherwise
identical modules that instantiate other identical modules in such a way that
the instance cannot be named via reflection would not be deduplicated because
the names of the instances would collide with the names of the modules in the
Builder.globalNamespace.

* Move blackbox verilog implementations within reach of verilator
Blackbox implementers can annotate the modules with information on where to get the source verilog
This API is very lightweight, real work is done in firrtl in companion PR
Added some verilog to BlackBoxTest.v resource for testing

* if a file named black_box_verilog_files.f exists add a
-f black_box_verilog_files.f to the verilog to cpp command

* [stevo]: add reset initialization to shift register

* [stevo]: better comment

* [stevo]: add tests, fix bug

Resolves #357
Also remove uses of firrtlToVerilog within chisel3.  Invoking Firrtl
programmatically is preferred to on the command line.  Update README to
indicate that Firrtl need not be installed.

Use the root project's unmanagedBase (".../lib") in all sub-projects.

Fixing a bug in passing down execution options to firrtl

* Name propagation

* chiselName everywhere at best-effort level

* Better collision handling

* Allow recursing into inner anonymous functions

* Add for loop and anonymous inner function tests

Record gives uses the power to create collections of heterogenous elements.
Bundle is a special case of Record that uses reflection to populate the
elements of the collection. Bundle also attempts to implement cloneType whereas
users of Record are required to supply one.

* Mark Annotation and FixedPoint as experimental
Fix tests and other references to these constructs

* Made experimental imports more specific where possible

* Make fromBits work with types other than UInt

* Oops, left in a println

* Add test for truncation/expansion

* Fix stuff that broke when FixedPoint fromBits PR was merged.

* Use .BP shorthand added in previous PR

Have FixedPoint use asFixedPoint in fromBits.