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Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

This avoids name aliasing with the chisel-template repository.

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Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Revert #3912 and #3825.

This reverts commit 35d3b710.
This reverts commit 386a7f35.

This is a follow-up to #3825.

MFC has attached a laebl "chisel3_builtin" to every ifElseFatal assertion.
Usually a label on ifElseFatal is just ignored but the label is emitted
when compiled with `-emit-chisel-asserts-as-sva`. So labels on assertions
converted from ifElseFatal disappear due to #3825. This PR restores labels
to preserve the old behavior.

Publishing appears to be using GPG from the runner image,
which is 2.2.27 not the 1.4.23 this action builds from source.
(which appears to be failing to build anyway)

Extends BorginUtils.bore (and related) to work where the source is a
probe.  Currently, if a user tries to do this, they will get an error
about being unable to probe a probe because the old code would
unconditionally wrap whatever the source was in `Probe`/`RWProbe`.  Change
this to not wrap if the source is already a probe.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This replaces printf-encoded assertion with ifElseFatal intrinsics.
The intrinsic is a private object of core since we don't want to expose it other than chisel3.assert.

Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>

* Support serializing Annotations to a Writer

Previous API serializing to a String is limited by JVM max size of 2 GiB
Strings.

* Serialize to Writer instead of String in WriteOutputAnnotations

* Pass FIRRTL annotations into `CIRCTConverter`
* add annotations lists to filter unknown annoations
* [cd] Bump CIRCT from firtool-1.66.0 to firtool-1.67.0

Co-authored-by: Asuna <SpriteOvO@gmail.com>
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: chiselbot <chiselbot@users.noreply.github.com>

Change logger annotations to mix-in the Unserializable trait so that they
will not emitted by a stage.  These annotations are not intended to be
seen by CIRCT and these should be stripped from the output FIRRTL text.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Change the way ChiselSim moves files to track and not move files which may
be duplicated in both the default black box filelist and in the main
CIRCT-produced filelist.  Previously, this was working because a java.nio
exception was being ignored.  However, this may have been hiding bugs
where the filelist was actually pointing at a file that did not exist.

This commit also does some heavy cleanup of the code for moving files to only
use java.nio methods as opposed to relying on doing string manipulations of
paths.  The logic is intended to be the exact same as before.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Previously, object circt.stage.ChiselStage was ignoring the Logger.
Also, Chisel was not creating its own logger scope which could lead to
clobbering of the Console when running invoking Chisel in the same
process multiple times.

Fix various places we had to workaround this behavior and fix tests
checking --log-level debug.

Add tests of additional ways that external modules could be included via
resources or paths.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Fix an incorrect assumption in ChiselSim that a 'filelist.f' will exist
that includes all modules, _including blackboxes_, in the design.  Change
this to try to also copy files from the black box filelist.  This makes
ChiselSim work with CIRCT 1.66 and earlier (which put everything in
'filelist.f') and CIRCT 1.66+ (which does not include blackboxes in
'filelist.f').

Note that this is intended as a temporary solution until FIRRTL has a rock
solid ABI that is implemented by CIRCT where all modules can be discovered
under an arbitrary public module.

See CIRCT changes here: https://github.com/llvm/circt/pull/6729



Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This tests that compilation with an external module works (as well as
testing that reading from a port driven from an external module
works---which doesn't provide any additional coverage).  This is
highlighting a problem in CIRCT beyond 1.66.0 where this relies on a
`filelist.f` file being produced which includes information about all
external modules.  This was dropped in a later commit [[1]] and needs to
be fixed.  This commit is intending to cause nightly to fail, demonstrate
the problem, and provide a check so that we know things are back to
working.

[1]: https://github.com/llvm/circt/pull/6729



Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Fix issues in docs that had public/main modules with uninferred widths.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* [core] Use format message on assume instead of when+printf-encoding.

This allows users to get a ClassType for use in other Property types,
which is especially useful when constructing aggregate Property types
of a specific Class.

It is shockingly annoying to get information out of ScalaTest here.

Also add Verilator instructions to install page.

---------

Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Use tabs to show mapping for releases by default, but include
prereleases in another tab.

Change the checking logic for the legality of a probe define destination
to align with FIRRTL specification language introduced recently [1].
Specifically, this enforces the following sentence:

> An operation that "writes" to a probe must be in a region whose layer
> color is enabled when the probe's layer color is enabled.

Previously, Chisel was more restrictive and would only allow writing to a
probe whose color was the same as the layer block you are currently in.
However, as has been worked out in CIRCT and elsewhere, it is fine to
drive a probe from any region that is enabled when the probe is also
enabled.

Practically, this gets some Chisel code passing that was legal by a FIRRTL
compiler, but Chisel was refusing to generate it.

CC: @rwy7

[1]: https://github.com/chipsalliance/firrtl-spec/commit/673aa08cc31883aa90eca5ceaa6bf0017f3165fa



Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This adds an API for integer Property shift right.