1. Mar 19, 2023
  2. Mar 17, 2023
  3. Mar 15, 2023
  4. Feb 23, 2023
  5. Feb 04, 2023
  6. Jan 31, 2023
    • mergify[bot]'s avatar
      Fix FIRRTL direction calculations for Vec and OpaqueType (backport #2956) (#2963) · 1f776d6c
      mergify[bot] authored
      * Fix calculuation of firrtl directions for Vecs
      
      For ports of type Vec, the direction of both the Vec itself and the
      direction of its elements can affect the direction of the FIRRTL port.
      Previously, we did not handle the fact that the Vec's elements could,
      themselves, be Vecs, thus making this directionality calculation
      recursive. Also, the logic was only applying to regular RawModules and
      Modules. The fix now applies to BlackBoxes and ExtModules as well.
      
      (cherry picked from commit b501b699)
      
      # Conflicts:
      #	core/src/main/scala/chisel3/RawModule.scala
      #	src/test/scala/chiselTests/Direction.scala
      
      * Fix calculation of firrtl directions for OpaqueTypes
      
      Similarly to Vecs, both the direction of the OpaqueType itself and the
      direction of its element can affect the direction of the resulting
      firrtl port. Since OpaqueTypes can wrap other OpaqueTypes, this
      direction calculation needs to be recursive. The same basic principle
      applies to calculating firrtl flip for OpaqueTypes that are elements of
      other Records.
      
      (cherry picked from commit c4ec45b3
      
      )
      
      # Conflicts:
      #	src/test/scala/chiselTests/RecordSpec.scala
      
      * Resolve backport conflicts
      
      ---------
      
      Co-authored-by: default avatarJack Koenig <koenig@sifive.com>
      1f776d6c
  7. Jan 28, 2023
  8. Jan 13, 2023
    • mergify[bot]'s avatar
      Support zero-width integer literals. (#2932) (#2938) · 135594a1
      mergify[bot] authored
      * assert{Inferred,Known}Width: tweak to support width of zero.
      
      Can't create -1.S(0.W), special-case zero-width.
      
      * Bits: nicer error messages for zero-width
      
      * Support zero-width integer literals.
      
      These are in the FIRRTL language specification now
      and supported by both SFC + MFC.
      
      For SInt, special-case handle zero-width as not needing a sign bit.
      
      Zero-width literals must be explicitly zero-width (`0.U(0.W)`);
      literals such as `0.U` are (still) at least 1-bit.
      
      * check zero-width to bool conversion
      
      * onehot test
      
      * UIntOps: test a few operations.
      
      * SIntOps: test a few operations
      
      * {S,U}IntOps: touchup test description, now includes head/tail/pad.
      
      * ChiselSpec: Fix assert{Known,Inferred}Width for zero-width.
      
      Specifically, fix the inferred-width check.
      
      Start from zero-width literal, otherwise 0.U will need 1 bit.
      
      * WidthSpec: update inferred zero-width test
      
      (cherry picked from commit fc3b4a08
      
      )
      
      Co-authored-by: default avatarWill Dietz <will.dietz@sifive.com>
      135594a1
  9. Jan 12, 2023
  10. Jan 10, 2023
  11. Dec 25, 2022
  12. Dec 20, 2022
  13. Dec 10, 2022
  14. Dec 09, 2022
  15. Dec 08, 2022
  16. Dec 07, 2022
  17. Dec 06, 2022
  18. Nov 30, 2022
    • mergify[bot]'s avatar
      Implement compressed Namespace (backport #2856) (#2860) · c21f31d0
      mergify[bot] authored
      * Implement compressed Namespace (#2856)
      
      The namespace disambiguates requests for the same name with _<idx>.
      Rather than storing every disambiguated name in the underlying HashMap,
      it now only stores the base along with the "next available" index. This
      makes the logic for checking if a name is already contained in the
      namespace slightly more sophisticated because users can name things in a
      way that will collide with disambiguated names from a common substring.
      
      For example, in naming the sequence "foo", "foo", "foo_1", the 2nd "foo"
      takes the name "foo_1" so the following "foo_1" gets disambiguated to
      "foo_1_1". But since we compressed that original "foo_1" into the same
      HashMap entry as just "foo", we have to do a form of "prefix checking"
      whenever naming something that ends in "_<idx>".
      
      In practice, the saved memory allocations more than make up for the more
      complicated logic to disambiguate names because the common case is still
      fast.
      
      (cherry picked from commit 1654d87a
      
      )
      
      # Conflicts:
      #	core/src/main/scala/chisel3/internal/Builder.scala
      
      * Resolve backport conflicts
      
      Co-authored-by: default avatarJack Koenig <koenig@sifive.com>
      c21f31d0
  19. Nov 15, 2022
  20. Nov 11, 2022
  21. Nov 09, 2022
  22. Nov 08, 2022
  23. Nov 06, 2022
  24. Nov 05, 2022
    • mergify[bot]'s avatar
      Add PartialDataView.supertype (backport #2826) (#2827) · 4149157d
      mergify[bot] authored
      * Add PartialDataView.supertype (#2826)
      
      This factory method makes it easy to create PartialDataViews from a
      Bundle type to its supertype. Because of the typing relationship, there
      is no need to provide a mapping between fields. The only thing necessary
      is to provide a function for constructing an instance of the supertype
      from an instance of the subtype.
      
      (cherry picked from commit 251d454a
      
      )
      
      # Conflicts:
      #	core/src/main/scala/chisel3/experimental/dataview/package.scala
      #	src/test/scala/chiselTests/experimental/DataView.scala
      
      * Resolve backport conflicts
      
      Co-authored-by: default avatarJack Koenig <koenig@sifive.com>
      4149157d
  25. Oct 25, 2022
  26. Oct 24, 2022