- Jun 15, 2021
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Adam Izraelevitz authored
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- Jun 09, 2021
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Jack Koenig authored
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- Jun 04, 2021
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Scala Steward authored
Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Scala Steward authored
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Scala Steward authored
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- Jun 02, 2021
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Jiuyang Liu authored
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- May 29, 2021
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Jiuyang Liu authored
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- May 27, 2021
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Scala Steward authored
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- May 26, 2021
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Jiuyang Liu authored
* spot a bug when BitPat width is 0 * fix #1919 Co-authored-by: -
Jiuyang Liu authored
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- May 21, 2021
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Scala Steward authored
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Scala Steward authored
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Martin Schoeberl authored
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- May 20, 2021
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Jiuyang Liu authored
* implement pla * implement test for pla * implement inverter matrix of PLA generator * fix for review. Co-authored-by:Boyang Han <yqszxx@gmail.com>
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Jiuyang Liu authored
* add os-lib to dependency. * implement EndToEndSMTBaseSpec * rename to SMTModelCheckingSpec * add documentation. * fix for review.
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- May 18, 2021
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Jiuyang Liu authored
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Scala Steward authored
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- May 17, 2021
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Scala Steward authored
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- May 15, 2021
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Scala Steward authored
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- May 12, 2021
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Scala Steward authored
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Scala Steward authored
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- May 11, 2021
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Scala Steward authored
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Scala Steward authored
* Update scalacheck-1-14, ... to 3.1.4.0 * Update scalacheck-1-14, ... to 3.1.4.0 * Update scalacheck-1-14 to 3.1.4.0 Co-authored-by: -
Scala Steward authored
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Jiuyang Liu authored
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- May 09, 2021
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Jiuyang Liu authored
* Add test to check ShiftRegister(s) with delay is 0. This should break ShiftRegister(x, 0) since last is not exist in a empty Seq. Originally, test only test 1 to 4, which missed a potential bug from #1723. * Fix ShiftRegister with 0 delay. if ShiftRegisters is empty, java will complain: ``` java.util.NoSuchElementException scala.collection.LinearSeqOptimized.last(LinearSeqOptimized.scala:150) ``` This fix this issue and return `in` directly when ShiftRegister size is 0. Co-authored-by:
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- May 07, 2021
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Scala Steward authored
Co-authored-by:Jiuyang Liu <liu@jiuyang.me>
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Jiuyang Liu authored
* add ShiftRegisters to expose register inside ShiftRegister. * use Seq.iter for oneline implementation.
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- May 06, 2021
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Schuyler Eldridge authored
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- May 05, 2021
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Scala Steward authored
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- Apr 30, 2021
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Jiuyang Liu authored
* add convert(chirrtl: cir.Circuit): fir.Circuit to convert chirrtl to firrtl. * add scaladoc. * add test. Co-authored-by: -
Jack Koenig authored
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Kevin Laeufer authored
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- Apr 29, 2021
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Scala Steward authored
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Scala Steward authored
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Scala Steward authored
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Scala Steward authored
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Scala Steward authored
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Megan Wachs authored
* Cookbook: clean up desiredName example * Update cookbook.md
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- Apr 28, 2021
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Chick Markley authored
This PR provides for support for Vec literals. They can be one of two forms Inferred: ``` Vec.Lit(0x1.U, 0x2.U) ``` or explicit: ``` Vec(2, UInt(4.W)).Lit(0 -> 0x1.U, 1 -> 0x2.U) ``` - Explicit form allows for partial, or sparse, literals. - Vec literals can be used as Register initializers - Arbitrary nesting (consistent with type constraints is allowed)
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