Change the upper type bound on the doNotDedup type parameter to
RawModule from LegacyModule (which is Module). This enables the
utility to be used on both MultiIOModule and RawModule.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Implemented by folding Element.ref into Data.ref. Element.ref had
special handling for literals, but because Bundles can also be literals,
there were code paths that tried to get the ref of a Bundle literal
which was non-existent. Now, all literals are handled together.

Because FIRRTL does not have support for Bundle literals, Bundle literal
refs are implemented by materializing a Wire.

* Improve source locators for switch statements.

The SecurityManager is global so is not thread-safe. This is the source
of flaky tests in FIRRTL CI.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Refine autonaming to have more intuitive behavior

Last name in an Expression wins, while the first Statement to name wins.
This is done via checking the _id of HasIds during autonaming and only
applying a name if the HasId was created in the scope of autonaming.
There is no change to .autoSeed or .suggestName behavior.

Behavior of chisel3-plugins from before this change is maintained.

* Update docs with naming plugin changes

This is a refinement of the assertion added in #1616 then removed in
 #1654. Because Records now set the refs of children upon binding,
later, unbound Records could incorrectly override the refs. The first
set should win.

It causes issues for some legal (if awkward) patterns. A larger refactor
of when refs are set could reinstate this check.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

This requires a combination of things, but it happens to be a
combination used by Diplomacy in Rocket Chip. It must be a Record in
compatibility code with Vecs as fields and a mix of components with and
without set directions.

* Fix crosslinks in mdoc. Can't use md suffix

* Removed all .md crossrefs

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Bugfix - module name collision for injecting aspect

* Fixed mechanism to avoid module name collisions

* Added comments for reviewer feedback

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Added forcename transform and tests

* Added documentation and additional error checking

* Added mdoc. Added RunFirrtlTransform trait

* Removed TODO comment

* Addressed reviewer feedback

* Removed trailing comma

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Causes issues when building the website, using these docs.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Use Data refs for name prefixing with aggregate elements

Vecs set the refs of their elements upon construction of those elements.
In the past, Records haven't set their elements refs until module close,
but it can be done sooner. Doing it upon binding means that refs will at
least be available for Records used in hardware elements. Since only
bound Data can be connected to anyway, Aggregate elements being
connected to will always have a ref which we can then use for creating
naming prefixes.

* Add tighter correctness checks

* Handle more cases in connection prefixing

Add support for forcing setRef to override a previous setting. This
is only used by BlackBox ports which need to drop their io prefix.

Also add a Try() around Data.bindingToString which sometimes throws
exceptions when being used to .toString a Data in an error message.

* Strip trailing spaces in names in compiler plugin

* Fix `-e` option causing ChiselStage.emit* to error

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Add test of `-e` ChiselStage behavior

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* fixup! Add test of `-e` ChiselStage behavior

This allows for sharing of the prefix stacks between Data, and removes a
boxing per prefix stack element that is no longer necessary.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Return 0.U for asUInt of a zero-element Seq

Add a condition to SeqUtils.asUInt to have it return an unspecified
width 0.U when applied to an empty sequence. This enables the ability
to do a Cat of a zero-element sequence.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Test elaboration of Cat on zero-element Seq

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Package chisel3 was not properly marked as an internal package so source
locators in reported errors would point to files like Bits.scala.

* ExtModule's lacked support built in support for providing
the verilog source. This changes creates traits that
can be used with ExtModule to provide the support currently found in
BlackBox

- Add support for ExtModule helpers
  - HasExtModuleResource to use addResource
  - HasExtModuleInline to use setInline
  - HasExtModulePath to use addPath
- Add tests of the above support.
  - Note: These tests use Stage instead of Driver
- Added ScalaDoc for HasBlackBoxInline#setInline

* Fix the danged trailing commas.

* Change to use `.transform` as the correct API for `ChiselStage`

Fixes #1606

Previously, the Data itself would be put on the prefix stack and its
full name would be used as the prefix for subsequent names. This meant
that prefixes would grow quadratically as the prefix is present both on
the Data pushed to the stack, and on the stack itself. This is fixed by
just using the "local" name of the Data being pushed on the stack.

A related issue is deferring the name resolution. This led to unintuitive
behavior when the name of a Data used as a prefix is overridden later
(usually when the Data is a return value). The overriding name would
show up in prefixes twice instead of once. It is much more intuitive to
grab the name at the moment of the connection creating the prefix rather
than deferring to later.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Fix broken mdoc

* Added test-chisel-docs to ci workflow

* Add requirement on build-treadle job

* Added forgotton colon

* Forgot cd into chisel3 dir

* moved three docs into explanations

* Updated reference

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

Change source and other relevant files to use SPDX license
LICENSE file moved from src/ to ./
Changed license file to refer to this per recommendation
using_spdx_license_list_short_identifiers

WARNING: Tests fail with as of yet undiagnosed error
```
[error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15
[error] Failed tests:
[error] 	chiselTests.QueueSpec
[error] 	examples.VendingMachineGeneratorSpec
[error] 	chiselTests.HarnessSpec
[error] 	chiselTests.ConnectSpec
[error] 	chiselTests.aop.SelectSpec
[error] 	chiselTests.PopCountSpec
[error] 	chiselTests.CloneModuleSpec
[error] (Test / test) sbt.TestsFailedException: Tests unsuccessful
[error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM
sbt:chisel3>
```

* Fix broken mdoc

* Added test-chisel-docs to ci workflow

Co-authored-by: Megan Wachs <megan@sifive.com>

Use caching to reduce number of expensive lookups

* Added documentation. Bugfix in plugin. Moved plugin APIs to separate package

* Revert reg naming behavior (omit underscore)

* Added documentation and a test

* Addressed reviewer feedback.

Test all cases in ParameterizedOneHotTesters

Co-authored-by: Jack Koenig <koenig@sifive.com>

ChiselCircuitAnnotation no longer extends CustomFileEmission, rather it
is Unserializable. Also the --chisel-output-file is added to the
ChiselCli.

New phase AddSerializationAnnotations constructs a
CircuitSerializationAnnotation from ChiselCircuitAnnotation and
ChiselOutputFileAnnotation. Both .fir and .pb file formats are
supported. Default format is .fir unless a --chisel-output-file is
specified with a .pb extension.

* fix loadMemoryFromFile to work with binary

Passed in hexOrBinary parameter to ChiselLoadMemoryAnnotation

* Added test for binary format support in loadMemoryFromFile

* Added test for binary format support in loadMemoryFromFile

Using JVM system properties sbt.sourcemode and sbt.workspace, one can now
easily build chisel3 with firrtl from source

Example use:

Assuming firrtl is cloned into the chisel3 root directory:
$ sbt -Dsbt.sourcemode=true -Dsbt.workspace=$PWD

Alternatively, one can set these properties in .sbtopts which can then
be committed, enabling building from source by default