Stop allowing Chisel users to describe circuits where a CHIRRTL memory
port escapes its when scope.  Previously, this was special-cased to
allow for existing Chisel standard library constructions to work.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Change the read with enable method on SyncReadMem to not return the
CHIRRTL mport.  This results in saner code generation in CHIRRTL where
the mport can't be used in subsequent code blocks.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Small changes to memory doc
- Fixed typo "except" => "accept"
- Use `Counter` explicitly in ROM section example.

* Fix counter doc compile error

* remove invisible doc block in memory example

* more small fixes to make mem example pass doc compile

* Get rid of sine wave iterator in memory doc

* get rid of tabs on VecInit example

* get rid of tabs on VecInit example

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Deborah Soung <debs@sifive.com>

Co-authored-by: Jack Koenig <koenig@sifive.com>

There are now more tool dependecies than just `verilator` to get the full test suite to pass. Also add instructions for running the tests without the compiler plugin,

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

The example in the README is a sum, not an average.

Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: Haoran Yuan <sinofp@tuta.io>
Co-authored-by: Boyang Han <yqszxx@gmail.com>

Fix CI.

PR #2023 fixed a composition issue for chisel3 biconnects delegating to
FIRRTL partial connect when compatibility mode Bundles are elements of
chisel3 Bundles. It missed an important case though that caused
previously working code to break.

The bug is fixed by doing the automatic flipping for compatibility mode
Bundles that have "Input" as a direction in addition to those that are
"Flipped".

This has been legal in FIRRTL since v1.2.3 (when reset inference started
using a unification-style algorithm) but was never exposed in the Chisel
API.

Also delete the overridden connects in AsyncReset and ResetType which
just duplicate logic from MonoConnect.

BiConnect in chisel3 delegates to FIRRTL <- semantics whenever it hits a
Bundle defined in `import Chisel._`. Because chisel3 <> is commutative
it needs to be mindful of flippedness when emitting a FIRRTL <- (which
is *not* commutative).

* Add @ekiwi's code as a starting point

* Add test for ChiselEnum isOneOf method

* Make isOneOfTester naming consistent with other testers

* Add scaladoc comments for isOneOf

* Add isOneOf tests that use the method that takes variable number of args

* Add guide level documentation example for isOneOf

Change the Scaladoc for the dontTouch utility.  Indicate that this is an
_optimization barrier_ and not just a guarantee that the signal won't be
removed.  The optimization barrier interpretation is the current
implementation in the Scala FIRRTL Compiler.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Also add newline to end of `verilog` modifier code blocks so that there
is always a newline between code blocks and following material.

Fix ChiselEnum warnings and use Logger for warnings instead of println

Previously, ChiselEnum would warn any time a UInt is converted to an
Enum. There was no way to suppress this warning. Now there is a factory
method (`.safe`) that does not warn and returns (Enum, Bool) where the
Bool is the result of calling .isValid on an Enum object. The regular
UInt cast is also now smarter and will not warn if all bitvectors of the
width of the Enum are legal states.

It also uses the same logger as the Builder so that if we ever refactor
that to be passed as an argument, it will be the same logger for both
Builder and warning reporting.

Fix aop.Select behavior for CloneModuleAsRecord

Previously, CloneModuleAsRecord clones would result in the same
BaseModule object coming up multiple times when using APIs like
.instances, .collectDeep, and .getDeep. This was not the intended
behavior and can lead to very subtle bugs.

* added to readme

* Update README.md

Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>

Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* deprecate getPorts with modulePorts.

* add doc to fullModulePorts and update deprecation notes.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Fix CloneModuleAsRecord support for .toTarget

* Add Clock
* Add Analog
* Add Interval
* Add line from User Types (...) to Record