Add a new BoringUtils method, also called "bore", that will go grab a
Data in a child and bring it up to the current module drilling any
necessary ports.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Rework Chisel internals to delay generation of Modules until all modules
are known.  This enables modules to make modifications to each other
because the modules have not closed yet.

Change instantiation to not populate a DefInstance with ports as the
ports are not known yet.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Remove the _compatAutoWrapPorts method as this does nothing.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Previously, the naming plugin would not recurse for the RHS of an
unapply, meaning that vals declared in blocks that ultimately return
some result that is unapplied into some named Data would not be named.

Also, audit and improve the naming mdocs.

* Added definition identifiers

A definition identifier is an eager, descriptive name that we can give module definitions. This is to help apply box-typing more generally in Chisel.

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Implement `typeName` API for a few `Data` types

* Fix silly compilation error

* Implement typeName API further for most data types and modules which need it

* Compilation error fixes

* Remove width parameter from Bool

* Test for Queue naming using typeNames

* Remove width-sensitive override for AsyncReset as it is irrelevant

* Add typeName for Analogs

* Add additional types to be tested

* Scalafmt

* Use circt ChiselStage

* Update queue naming of existing tests

* Scalafmt

* Change pipe desiredName to be consistent with other modules

* Update naming cookbook

* Update docs/src/cookbooks/naming.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Update docs/src/cookbooks/naming.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Add SInt to TypenameSpec

* Fix cookbook mdoc errors

* compileOnly tag on scala code

* More improvements of mdoc

* compileOnly -> compile-only

* Final mdoc review and fixes

* Add inferred UInt to test

---------

Co-authored-by: Megan Wachs <megan@sifive.com>

Deprecate ChiselStage$.elaborate as this exposes internal Chisel APIs,
namely "chisel3.internal.firrtl.Circuit".  Replace usages of this in
tests with emitCHIRRTL.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Change many tests from simulation-based to checking the CHIRRTL.
* Move tests that were hard to convert to new VecIntegrationSpec in
  integration-tests

Co-authored-by: Jack Koenig <koenig@sifive.com>

* mdoc-ify intrinsic explanation

* Update docs/src/explanations/intrinsics.md

* Update intrinsics.md

* IntModule

* intmodule works

* a bit of documentation

* formatting

* example and better test.  Rename all the things, now they are Blue!

* formatting

* typo

* move file

* indexes

* Update core/src/main/scala/chisel3/internal/firrtl/IR.scala

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

* Update docs/src/explanations/intrinsics.md

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

* Update docs/src/explanations/intrinsics.md

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

* simplify tests

---------

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

Change FIRRTL Circuit conversion/serialization to place
ChiselAnnotations (converted to FIRRTL Annotations) inside the FIRRTL
Circuit and to serialize this using the "%[[]]" inline JSON format that
is present in the FIRRTL spec.  This does not remove _all_ annotations
passed via the annotation file, but it is the first step towards that.

* Add low-level svsim based simulation to Chisel
* Add Peek/Poke API

Introduce `svsim`, a low level library for simulating SystemVerilog using Verilator and VCS. (#3121)

Also run formatting on SBT files.

Directly subclassing Iterable is lazy-ish, but if you call any operation
on the resulting value (eg. map or ++) it will evaluate the Iterable and
return a List.

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Use new private Record._elements to validate Record elements. This
allows us to check invariants earlier than on cloning or binding.

It seems that deprecations on methods that are macro expanded away do
not actually trigger a deprecation warning. Instead, we will just accept
no source locator on the deprecated API (no released version of Chisel
has the source locator).

It is a very painful change for users with marginal benefit. We plan to
change the package to chisel in the not-so-distant future--that's a much
better opportunity to make this change.

* overload MuxLookup.apply for EnumType
* remove MuxLookup.fromEnum
* add source locators to MuxLookup.apply using macros

These annotations are no longer used now that they cannot affect CIRCT
execution.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Make read-write inference on by default

Change CIRCT to turn on read-write inference by default.  This is
primarily done because this option was removed in:

  https://github.com/llvm/circt/commit/9620d656f8a59998cc38472a60f83bfdcb6a8549



Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Remove IMCP disable option for CIRCT

Remove the ability to disable inter-module constant propagation (IMCP) when
running with CIRCT.  This option was removed in:

  https://github.com/llvm/circt/commit/9620d656f8a59998cc38472a60f83bfdcb6a8549



Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

---------

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>